As noted in rtc_def.h, the tm_mon field in struct rtc_time is 1-12,
unlike in struct tm where it is 0-11. Currently, running "date" prints
the wrong

Date: 2020-04-01 (Friday)    Time: 13:05:30

and setting the RTC via the date command is also broken.
Signed-off-by: NRasmus Villemoes <rasmus.villemoes@prevas.dk>

Solved the overflow on phys_addr_t type for start + size in
mmu_set_region_dcache_behaviour() function.

This overflow is avoided by dividing start and end by 2 before addition,
and we only expecting that start and size are even.

This patch doesn't change the current function behavior if the
parameters (start or size) are not aligned on MMU_SECTION_SIZE.

For example, this overflow occurs on ARM32 with:
start = 0xC0000000 and size = 0x40000000
then start + size = 0x100000000 and end = 0x0.

For information the function behavior change with risk of regression,
if we just shift start and size before the addition.
Example with 2MB section size:
  MMU_SECTION_SIZE 0x200000 and MMU_SECTION_SHIFT = 21
  with start = 0x1000000, size = 0x1000000,
  - with the proposed patch, start = 0 and end = 0x1 as previously
  - with the more simple patch:
    end = (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT)
    the value of end change:
    start >> 21 = 0, size >> 21 = 0 and end = 0x0 !!!
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>

Add the new flags DCACHE_DEFAULT_OPTION to define the default
option to use according the compilation flags
CONFIG_SYS_ARM_CACHE_*.

This new compilation flag allows to simplify dram_bank_mmu_setup()
and can be used as third parameter (option=dcache option to select)
of mmu_set_region_dcache_behaviour function.
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>

Add protection in dram_bank_mmu_setup() to avoid access to bd->bi_dram
before relocation.

This patch allow to use the generic weak function dram_bank_mmu_setup
to activate the MMU and the data cache in SPL or in U-Boot before
relocation, when bd->bi_dram is not yet initialized.

In this cases, the MMU must be initialized explicitly with
mmu_set_region_dcache_behaviour function.
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>

Move CONFIG_SYS_ARM_CACHE_WRITETHROUGH and
CONFIG_SYS_ARM_CACHE_WRITEALLOC into Kconfig done by moveconfig.py.

Kconfig uses a choice between the 3 values supported in U-Boot,
including the new configuration CONFIG_SYS_ARM_CACHE_WRITEBACK
(the default configuration).

The patch also avoids to select simultaneously 2 configurations.
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>

The most basic printf("%i", value) formating string was missing,
add it for the sake of convenience.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>

- distro boot support for SPI flash
- sifive spi flash driver

Pull request for UEFI sub-system for efi-2020-07-rc2

This pull request contains bug fixes needed due to the merged changes for
EFI secure boot.

Patches are supplied to identify EFI system partitions.

HiFive Unleashed A00 support is25wp256 spi-nor flash,
So enable the same and add test result log for future
reference.

Tested on SiFive FU540 board.

Thanks to Sagar for various use cases and tests.

[QUAD mode in dt with spi-tx-bus-width: <4>]
 pp opcode      = 0x34 [QUAD MODE]
 read opcode  = 0x6c  [QUAD MODE]
 erase opcode = 0x21

SPI-NOR:
1. erase entire flash: Pass
2. write entire flash: Pass
3. read entire flash: Pass
4. cmp 32MiB read back data: Pass
5. MMC: Booted Linux and dtb from mmc

[SPI MODE in dt with spi-tx-bus-width: <1>]
pp opcode     = 0x12 [SPI MODE]
read opcode  = 0xc   [SPI MODE]
erase opcode = 0x21

SPI-NOR:
1. erase entire flash: Pass
2. write entire flash: Pass
3. read entire flash: Pass
4. cmp 32MiB read back data: Pass
5. MMC: Booted Linux and dtb from mmc
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Tested-by: NSagar Kadam <sagar.kadam@sifive.com>

Add U-Boot specific dts file for hifive-unleashed-a00, this
would help to add u-boot specific properties and other node
changes without touching the base dts(i) files which are easy
to sync from Linux.

Added spi2 alias for qspi2 as an initial u-boot specific
property change.

spi probing in current dm model is very much rely on aliases
numbering. Even though the qspi2 can't come under any associated
spi nor flash it would require to specify the same to make proper
binding happen for other spi slaves.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Tested-by: NSagar Kadam <sagar.kadam@sifive.com>

The guessed reason is that the existing logic of filling
tx fifo with data, rx fifo with NULL for tx transfer and
filling rx fifo with data, tx fifo with NULL for rx transfer
is not clear enough to support the Quad Page Program.
   
SiFive SPI controllers have specific sets of watermark
registers and SPI I/O directions bits in order to program
SPI controllers clear enough to support all sets of operating
modes.
   
Here is the exact programing sequence that would follow on this
patch and tested via SPI-NOR and MMC_SPI.
   
- set the frame format proto, endian
- set the frame format dir, set it for tx and clear it for rx
- TX transfer:
  fill tx fifo with data.
  wait for TX watermark bit to clear.
- RX transfer:
  fill tx fifo with 0xff.
  write nbytes to rx watermark register
  wait for rx watermark bit to clear.
  read the rx fifo data.

So, this patch adopts this program sequence and fixes the existing
I/O direction bit.

Cc: Vignesh R <vigneshr@ti.com>
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Tested-by: NSagar Kadam <sagar.kadam@sifive.com>

SiFive SPI controller has a proto bit field in frame format
register which would be used to configure the SPI I/O protocol
lines used on specific transfer. 

Right now the driver is configuring this proto using slave->mode,
for all types of transctions. This makes the driver unable to
function since the proto needs to configure dynamically for
each and every transaction separately at runtime.

Now, the controller driver supports per transfer via spi-mem
exec_opo, so add the fmt_proto flag and fill the per transfer
buswidth so that the controller configures the proto bit at
runtime.

This patch fixes the SPI controller works with SPI NOR flash
on quad read with page program.

Cc: Vignesh R <vigneshr@ti.com>
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Tested-by: NSagar Kadam <sagar.kadam@sifive.com>

SiFive SPI controller is responsible to handle the
slave devices like mmc spi and spi nor flash.

The controller is designed such a way that it would
handle the slave transactions based on the I/O protocol
numbers, example if spi nor slave send quad write opcode
it has to send alone with I/O protocol number of 4 and
if it try to send data it has to send I/O protocol number
along with 4 line data.

But the current spi-xfer code from spi-mem is combining
the opcode and address in a single transaction, so the
SPI controller will be unable to identify the I/O protocol
number of opcode vs address.

So, add the spi-mem exec_op with spi-xfer of opcode, address
and data as a separate transaction. This doesn't remove
the .xfer of dm_spi_ops since mmc spi will make use of it.

Note: This code might have moved to the spi-mem core area
once we have done the dedicated tests on other controllers
and have real reason to move.

Cc: Vignesh R <vigneshr@ti.com>
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Tested-by: NSagar Kadam <sagar.kadam@sifive.com>

Spansion "s25fs512s" flash is incorrectly decoded as "s25fl512s" on
various platforms as former is not present. Add the entry.

Linux already has both the flashes present. A snippet below:
{ "s25fl512s",  INFO6(0x010220, 0x4d0080, 256 * 1024, 256...},
{ "s25fs512s",  INFO6(0x010220, 0x4d0081, 256 * 1024, 256...},
Signed-off-by: NKuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>

Enable designware watchdog driver for rk3399 if WDT defined.

Cc: Marek Vasut <marex@denx.de>
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>

IS25WP256 flash chips do support 4byte address opcodes,
so enable support for it.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NSagar Kadam <sagar.kadam@sifive.com>

Enable QE bit for ISSI flash chips.

QE enablement logic is similar to what Macronix
has, so reuse the existing code itself.

Cc: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>

Usually variable name slave is used for spi_slave structure
and slave_plat for the dm_spi_slave_platdata.

Let's follow this meaningful notation by replacing slave
with slave_plat for dm_spi_slave_platdata structure.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Enable SPI flash(SF) distro boot command in rk3399.

This distro boot will read the boot script at specific
location at the flash and start sourcing the same.

Included the SF device at the last of the target devices
list since all the rest of the devices on the list have
more possibility to boot the distribution due to the
size of the SPI flash is concern.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>

- DM ACPI support (Part A)
- Improve support for chain-loading x86 U-Boot

Xilinx changes for v2020.07-rc2

mmc:
- Fix dt property handling via generic function

clk:
- Fix versal watchdog clock setting

nand:
- Fix zynq nand command comparison

xilinx:
- Enable ubifs
- Sync board_late_init configurations with initrd_high setup
- Make custom distro boot more verbose

zynq:
- Kconfig alignments
- Fix nand cse configuration

zynqmp:
- Fix zcu104 low level qspi configuration
- Small DT updates
Signed-off-by: NTom Rini <trini@konsulko.com>

- Add DM_ETH support for DPAA1, DPAA2 based RDB platforms: ls1046ardb,
  ls1043ardb, lx2160ardb, ls2088ardb, ls1088ardb.
- Add GICv3 support for ls1028a, ls2088a, ls1088a.
- Add lpuart support on ls1028aqds.
- Few bug fixes and updates on ls2088a, ls1012a, ls1046a, ls1021a based
  platforms.

Add a few notes about this feature, which is aimed for development.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

With chromebook_coral we normally run TPL->SPL->U-Boot. This is the
'bare metal' case.

When running from coreboot we put u-boot.bin in the RW_LEGACY portion
of the image, e.g. with:

   cbfstool image-coral.serial.bin add-flat-binary -r RW_LEGACY \
	-f /tmp/b/chromebook_coral/u-boot.bin -n altfw/u-boot \
	-c lzma -l 0x1110000 -e 0x1110000

In this case U-Boot is run from coreboot (actually Depthcharge, its
payload) so we cannot access CAR. Use the existing stack instead.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

If U-Boot is running from coreboot we need to skip low-level init. Add
an way to detect this and to set the gd flag.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

To support detecting booting from coreboot, move the code which locates
the coreboot tables into a common place. Adjust the algorithm slightly to
use a word comparison instead of string, since it is faster.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
[bmeng: correct the comments to 960KB]
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>

When U-Boot is run from another boot loader, much of the low-level init
needs to be skipped.

Add a flag for this and adjust ll_boot_init() to use it.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NPeng Fan <peng.fan@nxp.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

When U-Boot is not the first-stage bootloader we don't want to
re-configure the PCI devices, since this has already been done. Add a
check to avoid this.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

When U-Boot is not the first-stage bootloader the interrupt and cache init
must be skipped, as well as init for various peripherals. Update the code
to add checks for this.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

When U-Boot is not the first-stage bootloader the FSP-S init must be
skipped. Update it to add a check.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

It is useful to be able to boot the same x86 image on a device with or
without a first-stage bootloader. For example, with chromebook_coral, it
is helpful for testing to be able to boot the same U-Boot (complete with
FSP) on bare metal and from coreboot. It allows checking of things like
CPU speed, comparing registers, ACPI tables and the like.

When U-Boot is not the first-stage bootloader much of this code is not
needed and can break booting. Add checks for this to the FSP code.

Rather than checking for the amount of available SDRAM, just use 1GB in
this situation, which should be safe. Using 2GB may run into a memory
hole on some SoCs.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

It is useful to dump ACPI tables in U-Boot to see what has been generated.
Add a command to handle this.

To allow the command to find the tables, add a position into the global
data.

Support subcommands to list and dump the tables.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>

Put this in the context along with the other important pointers.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>

We always write three basic tables to ACPI at the start. Move this into
its own function, along with acpi_fill_header(), so we can write a test
for this code.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Move this code to a generic location so that we can test it with sandbox.
This requires adding a few new fields to acpi_ctx, so drop the local
variables used in the original code.

Also use mapmem to avoid pointer-to-address casts which don't work on
sandbox.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>

We don't actually support tables without an XSDT so we can drop this dead
code.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>

Call the new core function to permit devices to write their own ACPI
tables. These tables will appear after all other tables.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>

The current code uses an address but a pointer would result in fewer
casts. Also it repeats the alignment code in a lot of places so this would
be better done in a helper function.

Update write_acpi_tables() to make use of the new acpi_ctx structure,
adding a few helpers to clean things up.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>

A device may want to write out ACPI tables to describe itself to Linux.
Add a method to permit this.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NWolfgang Wallner <wolfgang.wallner@br-automation.com>

Devices need to report various identifiers in the ACPI tables. Rather than
hard-coding these in drivers it is typically better to put them in the
device tree.

Add a binding file to describe this.
Signed-off-by: NSimon Glass <sjg@chromium.org>