Support system clocks for LD4, Pro4, sLD8, Pro5, PXs2/LD6b, LD11, LD20.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The R8A7795 and R8A7796 tables use different constants to identify
clock in DT, so split the tables and use the correct constants on
R8A7795. This fixes UART clock misconfiguration on R8A7795.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

This SoC is too old.  It is difficult to maintain any longer.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Since commit f0776a55 ("spl: dm: Kconfig: SPL_CLK depends on
SPL_DM"), the following warning is displayed:

  $ make uniphier_v8_defconfig
  warning: (ARCH_ZYNQ && ARCH_ZYNQMP && STM32F7 && CLK_UNIPHIER) selects
  SPL_CLK which has unmet direct dependencies (CLK && SPL_DM)

While I am here, I am removing the prompt to make it user-unconfigurable
option so that "select CLK_UNIPHIER" can be omitted.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Use DIV_ROUND_UP instead RATE_TO_DIV for all Rockchip SoC
clock driver.
Add or fix the div-field overflow check at the same time.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

dwmmc controller has default internal divider by 2,
and we always provide double of the clock rate request by
dwmmc controller. Sync code for all Rockchip SoC with:
4055b46 rockchip: clk: rk3288: fix mmc clock setting
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixup for 'missing DIV_ROUND_UP' conflict for clk_rk3288.c:]
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

As SPI support may be useful in the boot-flow, this adds support for
configuring the SPI controller's clocks in the RK3368 clock driver.
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

With the clock support in rk3368_clk_set_rate() conditionalized on
various feature definitions, 'priv' can remain unused (e.g. in the
SPL build when only MMC is enabled).
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

To enable the GMAC on the RK3368, we need to set up the clocking
appropriately to generate a tx_clk for the MAC.

This adds an implementation that implements the use of the <&ext_gmac>
clock (i.e. an external 125MHz clock for RGMII provided by the PHY).
This is the clock setup used by the boards currently supported by
U-Boot (i.e. Geekbox, Sheep and RK3368-uQ7).

This includes the change from commit
 - rockchip: clk: rk3368: define GMAC_MUX_SEL_EXTCLK
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

As part of the DRAM initialisation process (running as part of the TPL
stage) on the RK3368, we need to set up the DRAM PLL.

This implements support for configuring the PLL to for 1200, 1332 or
1600 MHz (i.e. for DDR3-1200, DDR3-1333, DDR3-1600 operating modes).
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

The original clock support for MMC/SD cards on the RK3368 suffered
from a tendency to select a divider less-or-equal to the the one
giving the requested clock-rate: this can lead to higher-than-expected
(or rather: higher than supported) clock rates for the MMC/SD
communiction.

This change rewrites the MMC/SD clock generation to:
 * always generate a clock less-than-or-equal to the requested clock
 * support reparenting among the CPLL, GPLL and OSC24M parents to
   generate the highest clock that does not exceed the requested rate

In addition to this, the Linux DTS uses HCLK_MMC/HCLK_SDMMC instead of
SCLK_MMC/SCLK_SDMMC: to match this (and to ensure that clock setup
always works), we adjust the driver appropriately.

This includes the changes from:
 - rockchip: clk: rk3368: convert MMC_PLL_SEL_* definitions to shifted-value form
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

To implement a TPL stage (incl. its DRAM controller setup) for the
RK3368, we'll want to configure the DPLL (DRAM PLL).

This commit implements setting the DPLL (CLK_DDR) and provides PLL
configuration details for the common DRAM operating speeds found on
RK3368 boards.
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

The RK3368 has a somewhat temperamental BootROM (which I learned the
hard way) when it comes to reconfiguring the CPLL and GPLL (in fact,
experiments show that changing the GPLL broke things for me, while
changing the CPLL seems to be more benign).  These should not be
modified by the SPL stage, if we intend to return to the BootROM for
chain booting the next stage.

This commit changes the clock initialisation to not change CPLL/GPLL
before returning to the BootROM (i.e. in TPL).  As it's safe to change
these settings if we no longer intend to return to U-Boot, we'll run
the full PLL setup a little later (i.e. in SPL).
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

With the RK3368's limited TPL size, we'll want to use OF_PLATFDATA for
the SPL stage.  This implements support for OF_PLATDATA in the clock
driver for the RK3368.
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

The RK3368 TRM recommends to configure the bandwith adjustment (CON2)
for PLLs to NF/2.  This implements this for all reconfigurations of
PLLs and removes the 'has_bwadj' flag (as the RK3368 always has the
bandwidth-adjustment feature according to its manual).
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Introduce TPL_CLK to allow finer-grained selection of TPL features
for feature-rich (i.e. DM-based) TPL stages.
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NTom Rini <trini@konsulko.com>

SPL_CLK should also depend on SPL_DM (and not just on CLK).
Add the additional dependency.
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NTom Rini <trini@konsulko.com>

Add clock driver for the RCar Gen3 R8A7795 and R8A7796 SoCs .
This driver allows reading out the clock configuration set by
previous boot stages and enabling and disabling clock using
the MSTP registers. Setting clock is not supported thus far.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

These macros and one variable is not used anywhere that's why
they should be removed.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Dont panic incase of mmio write/read failures instead return
error and let the peripheral driver take care of clock get
and set failures.
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Add support for CCF, this CCF reads the ref clocks
from dt and checks all the required clock control
registers for its source , divisors and calculates
the clock from them. This supports clock and set
functions.

Panic when read/write fails.
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Move clk_release_all() prototype and definition inside
OF_CONTROL flag to avoid following compilation error for
poplar platform:

aarch64:  +   poplar
+drivers/usb/host/built-in.o: In function `ehci_usb_remove':
+drivers/usb/host/ehci-generic.c:159: undefined reference to `clk_release_all'
+drivers/usb/host/built-in.o: In function `ehci_usb_probe':
+drivers/usb/host/ehci-generic.c:133: undefined reference to `clk_release_all'
+make[1]: *** [u-boot] Error 139
+make: *** [sub-make] Error 2

Introduced by 4e542c4 clk: add clk_release_all()
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>

Add clk_release_all() method which Disable/Free an
array of clocks that has been previously requested by
clk_request/get_by_*()
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

The clk driver for the RK3368 picked the wrong data structure's size
for its auto-alloc size: the size was calculated on the structure
representing the CRU hardware block instead of the priv structure.
As the CRU's register file is much larger than the driver's priv,
this did not cause any pain (except wasting memory).

Fix this by using the correct data structure's size.
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

All drivers which was using clock_get() are now using
clk_get_rate() from clock framework, now it's safe to
remove clock_get().
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Acked-by: NVikas MANOCHA <vikas.manocha@st.com>

clean the code by removing unused enums, structs and
defines related to clocks
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Acked-by: NVikas MANOCHA <vikas.manocha@st.com>

Add clock framework .get_rate callback.
This step will allow to convert all drivers which was using
proprietary clock_get() to use clock framework .get_rate().
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Acked-by: NVikas MANOCHA <vikas.manocha@st.com>

Retrieve RCC base address from DT, this will prepare
the ground for future STM32 SoCs support.
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Acked-by: NVikas MANOCHA <vikas.manocha@st.com>

Also remove its declaration from stm32.h which
is no more needed.
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Acked-by: NVikas MANOCHA <vikas.manocha@st.com>

Add clock driver init support for:
- cpu, bus clock init;
- emmc, sdmmc clock;
- ddr clock;
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Fixed format specified (%x -> %p) in clk_rk322x.c:
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

Fix warnings reported by sparse:
 - ... was not declared. Should it be static?"
 - cast to restricted __be32

While fixing those, the type conflict of cci500_init() was found.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

According to rk3036 TRM, pll_con1[12] should be set to '1' for the pll
integer mode, while the '0' means the frac mode.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

The variables gpll_init_cfg and apll_init_cfg are unused in this file,
remove them.

Cc: Simon Glass <sjg@chromium.org>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Detect with a previous boot loader has already set up the clocks and set
them up again so that U-Boot gets what it expects.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Shifted masks are the standard approach with rockchip since it allows
use of the mask without shifting it each time. Update the definitions and
the driver to match.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Add clock driver support for Rockchip rv1108 soc
Signed-off-by: NAndy Yan <andy.yan@rock-chips.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

- hclk/pclk_div range　should use '<=' instead of '<'
- use GPLL for pd_bus clock source
- pd_bus HCLK/PCLK clock rate should not bigger than ACLK
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Embeded the shift in mask MACRO definition in cru header file
and clock driver.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Add driver to setup the various PLLs and peripheral
clocks on the RK3368.
Signed-off-by: NAndy Yan <andy.yan@rock-chips.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Update the fixed-rate clock driver to support a live device tree.
Signed-off-by: NSimon Glass <sjg@chromium.org>