- 07 7月, 2014 3 次提交
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由 Hans de Goede 提交于
The DMA code in sunxi_mmc.c is broken. mmc_trans_data_by_dma() allocates the dma descriptors on the stack, and then exits while the dma transfer is in progress, so the dma engine is reading stack memory which at that point may be re-used. So far we've gotten away with this by luck, but recent u-boot changes have shifted the stack start address by 16 bytes, which combined with dma alignment now exposes this problem. Since we end up just busy waiting for the dma engine anyway, this commit fixes things by simply removing the dma code, resulting in smaller bug-free code. Signed-off-by: NHans de Goede <hdegoede@redhat.com> Acked-by: NIan Campbell <ijc@hellion.org.uk>
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由 Hans de Goede 提交于
Adjust the u-boot-spl.lds linker script to match the changes made in the 41623c91 "arm: move exception handling out of start.S files" commit. Signed-off-by: NHans de Goede <hdegoede@redhat.com> Acked-by: NIan Campbell <ijc@hellion.org.uk>
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由 Hans de Goede 提交于
We should not be aligning the amount of bytes which we try to read from the disk, this leads to trying to read more bytes then there are which fails. file_size is already aligned to BLOCK_SIZE before being stored in img.header.length, so there is no need for load_size at all. Signed-off-by: NHans de Goede <hdegoede@redhat.com> Acked-by: NIan Campbell <ijc@hellion.org.uk>
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- 05 7月, 2014 15 次提交
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由 Chin Liang See 提交于
To move the arch common function away from board folder to arch/arm/cpu/armv7/socfpga folder. Its to avoid code duplication for other non Altera dev kit which is using socfpga device. Signed-off-by: NChin Liang See <clsee@altera.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Acked-by: NDetlev Zundel <dzu@denx.de>
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由 Linus Walleij 提交于
Turn on generic board for the integrators, as per the request in the startup message. Everything just works, tested on the Integrator/AP and Integrator/CP. Signed-off-by: NLinus Walleij <linus.walleij@linaro.org> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Stephen Warren 提交于
Serial port, SD card, and LCD all work. Signed-off-by: NStephen Warren <swarren@wwwdotorg.org> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Christian Riesch 提交于
Signed-off-by: NChristian Riesch <christian.riesch@omicron.at>
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由 Shaibal.Dutta 提交于
Fix following compilation error when CONFIG_ARM64 is defined Error: unknown or missing system register name at operand 2 -- `mrs x0,daifmsr daifset,#3' Signed-off-by: NShaibal.Dutta <shaibal.dutta@broadcom.com> Signed-off-by: NDarwin Rambo <drambo@broadcom.com> Reviewed-by: NDarwin Rambo <drambo@broadcom.com>
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由 Łukasz Dałek 提交于
Enable 'generic board init' for H2200 palmtop. Signed-off-by: NLukasz Dalek <luk0104@gmail.com> Acked-by: NMarek Vasut <marex@denx.de>
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由 Jeroen Hofstee 提交于
cc: Tom Rini <trini@ti.com> Signed-off-by: NJeroen Hofstee <jeroen@myspectrum.nl>
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由 Albert ARIBAUD 提交于
Run tools/reformat.py -i -d '-' -s 8 to reorder boards as header comments suggest
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由 Chin Liang See 提交于
Scan Manager driver will be called to configure the IOCSR scan chain. This configuration will setup the IO buffer settings Signed-off-by: NChin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Wolfgang Denk <wd@denx.de> CC: Pavel Machek <pavel@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
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由 Chin Liang See 提交于
To enable the DesignWare watchdog support at SOCFPGA Cyclone V dev kit. Signed-off-by: NChin Liang See <clsee@altera.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@ti.com>
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由 Chin Liang See 提交于
To add the DesignWare watchdog driver support. It required information such as register base address and clock info from configuration header file within include/configs folder. Signed-off-by: NChin Liang See <clsee@altera.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@ti.com>
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由 Sergey Kostanbaev 提交于
This patch returns back support for old ep93xx processors family Signed-off-by: NSergey Kostanbaev <sergey.kostanbaev@gmail.com> Cc: albert.u.boot@aribaud.net
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由 Axel Lin 提交于
In current gpio_set_value() implementation, it always sets the gpio control bit no matter the value argument is 0 or 1. Thus the GPIOs never set to low. This patch fixes this bug. The address bus is used as a mask on read/write operations, so that independent software drivers can set their GPIO bits without affecting any other pins in a single write operation. Thus we don't need a read-modify-write to update the register. Signed-off-by: NAxel Lin <axel.lin@ingics.com> Acked-by: NStefan Roese <sr@denx.de> Reviewed-by: NVipin Kumar <vipin.kumar@st.com> Reviewed-by: NMichael Trimarchi <michael@amarulasolutions.com>
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由 Jeroen Hofstee 提交于
This is not only more readable but also prevents a warning about a missing prototype. The prototypes which are actually missing are added. cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: NJeroen Hofstee <jeroen@myspectrum.nl> Reviewed-by: NTom Rini <trini@ti.com>
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由 York Sun 提交于
LS2085A is an ARMv8 implementation. This adds board support for emulator and simulator: Two DDR controllers UART2 is used as the console IFC timing is tightened for speedy booting Support DDR3 and DDR4 as separated targets Management Complex (MC) is enabled Support for GIC 500 (based on GICv3 arch) Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NArnab Basu <arnab.basu@freescale.com> Signed-off-by: NJ. German Rivera <German.Rivera@freescale.com> Signed-off-by: NBhupesh Sharma <bhupesh.sharma@freescale.com>
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- 03 7月, 2014 7 次提交
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由 J. German Rivera 提交于
Adding support to load and start the Layerscape Management Complex (MC) firmware. First, the MC GCR register is set to 0 to reset all cores. MC firmware and DPL images are copied from their location in NOR flash to DDR. MC registers are updated with the location of these images. Deasserting the reset bit of MC GCR register releases core 0 to run. Core 1 will be released by MC firmware. Stop bits are not touched for this step. U-boot waits for MC until it boots up. In case of a failure, device tree is updated accordingly. The MC firmware image uses FIT format. Signed-off-by: NJ. German Rivera <German.Rivera@freescale.com> Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NLijun Pan <Lijun.Pan@freescale.com> Signed-off-by: NShruti Kanetkar <Shruti@Freescale.com>
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由 York Sun 提交于
Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NVarun Sethi <Varun.Sethi@freescale.com> Signed-off-by: NArnab Basu <arnab.basu@freescale.com>
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由 York Sun 提交于
Make MMU function reusable. Platform code can setup its own MMU tables. Signed-off-by: NYork Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn>
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由 J. German Rivera 提交于
This is needed for accessing peripherals with 64-bit MMIO registers, from ARMv8 processors. Signed-off-by: NJ. German Rivera <German.Rivera@freescale.com>
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由 Darwin Rambo 提交于
The armv8 ARM Trusted Firmware (ATF) can be used to load various ATF images and u-boot, and does this for virtual platforms by using semihosting. This commit extends this idea by allowing u-boot to also use semihosting to load the kernel/ramdisk/dtb. This eliminates the need for a bootwrapper and produces a more realistic boot sequence with virtual models. Though the semihosting code is quite generic, support for armv7 in fastmodel is less useful due to the wide range of available silicon and the lack of a free armv7 fastmodel, so this change contains an untested armv7 placeholder for the service trap opcode. Please refer to doc/README.semihosting for a more detailed description of semihosting and how it is used with the armv8 virtual platforms. Signed-off-by: NDarwin Rambo <drambo@broadcom.com> Cc: trini@ti.com Cc: fenghua@phytium.com.cn Cc: bhupesh.sharma@freescale.com
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由 Tom Rini 提交于
Signed-off-by: NTom Rini <trini@ti.com>
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- 02 7月, 2014 9 次提交
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由 Stephen Warren 提交于
Almost all of ci_udc.c uses variable name "ep" for a struct usb_ep and "ci_ep" for a struct ci_ep. This is nice and consistent, and helps people know what type a variable is without searching for the declaration. handle_ep_complete() doesn't do this, so fix it to be consistent. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
A UDC's alloc_request method should zero out the newly allocated request. Ensure the Atmel driver does so. This issue was found by code inspection, following the investigation of an intermittent issue with ci_udc, which was tracked down to failing to zero out allocated requests following some of my changes. All other UDC drivers already zero out requests in one way or another. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
struct ci_req is a purely software structure, and needs no specific memory alignment. Hence, allocate it with calloc() rather than memalign(). The use of memalign() was left-over from when struct ci_req was going to hold the aligned bounce buffer, but this is now dynamically allocated. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
There's no need to store an array of QTD pointers in the controller. Since the calculation is so simple, just have ci_get_qtd() perform it at run-time, rather than pre-calculating everything. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
2 QTDs are allocated for each EP. The current allocation scheme aligns the first QTD in each pair, but simply adds the struct size to calculate the second QTD's address. This will result in a non-cache-aligned addresss IF the system's ARCH_DMA_MINALIGN is not 32 bytes (i.e. the size of struct ept_queue_item). Similarly, the original ilist_ent_sz calculation aligned the value to ARCH_DMA_MINALIGN but didn't take the USB HW's 32-byte alignment requirement into account. This doesn't cause a practical issue unless ARCH_DMA_MINALIGN < 32 (which I suspect is quite unlikely), but we may as well fix the code to be explicit, so it's obviously completely correct. The new value of ILIST_ENT_SZ takes all alignment requirements into account, so we can simplify ci_{flush,invalidate}_qtd() by simply using that macro rather than calling roundup(). Similarly, the calculation of controller.items[i] can be simplified, since each QTD is evenly spaced at its individual alignment requirement, rather than each pair being aligned, and entries within the pair being spaced apart only by structure size. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
This will allow functions other than ci_udc_probe() to make use of the constants in a future change. This in turn requires converting the const int variables to #defines, since the initialization of one global const int can't depend on the value of another const int; the compiler thinks it's non-constant if that dependency exists. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
Fix ci_ep_submit_next_request()'s ZLP transmission code to explicitly call ci_get_qtd() to find the address of the other QTD to use. This will allow us to correctly align each QTD individually in the future, which may involve leaving a gap between the QTDs. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
ci_udc_probe() initializes a pair of QHs and QTDs for each EP. After each pair has been initialized, the pair is cache-flushed. The conversion from QH/QTD index [0..2*NUM_END_POINTS) to EP index [0..NUM_ENDPOINTS] is incorrect; it simply subtracts 1 (which yields the QH/QTD index of the first entry in the pair) rather than dividing by two (which scales the range). Fix this. On my system, this avoids cache debug prints due to requests to flush unaligned ranges. This is caused because the flush calls happen before the items[] array entries are initialized for all but EP0. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Albert ARIBAUD 提交于
Conflicts: boards.cfg Conflict was trivial between goni maintainer change and lager_nor removal.
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- 01 7月, 2014 4 次提交
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由 Albert ARIBAUD 提交于
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由 Albert ARIBAUD 提交于
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由 Albert ARIBAUD 提交于
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由 Albert ARIBAUD 提交于
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- 30 6月, 2014 1 次提交
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由 Przemyslaw Marczak 提交于
Robert Baldyga will now take care of this board. Signed-off-by: NPrzemyslaw Marczak <p.marczak@samsung.com> Cc: Robert Baldyga <r.baldyga@samsung.com> Acked-by: NLukasz Majewski <l.majewski@samsung.com> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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- 26 6月, 2014 1 次提交
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由 Fabio Estevam 提交于
With CONFIG_SYS_GENERIC_BOARD the board hangs after issuing a 'save' command. Remove CONFIG_SYS_GENERIC_BOARD until this issue can be fixed properly. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
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