- 15 5月, 2013 19 次提交
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由 York Sun 提交于
Separate CONFIG_PPC_T4240 from board config file. Prepare to add more SoC variants supported on the same board. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 York Sun 提交于
T4160 SoC is low power version of T4240. The T4160 combines eight dual threaded Power Architecture e6500 cores and two memory complexes (CoreNet platform cache and DDR3 memory controller) with the same high-performance datapath acceleration, networking, and peripheral bus interfaces. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 York Sun 提交于
Protocols are constants. Fix arrays with const prefix. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 York Sun 提交于
The PIR parsing algorithm we used is not only for E6500. It applies to all SoCs with chassis 2. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 York Sun 提交于
Use decimal and hexadecimal for protocol numbers. It helps to match with SoC user manual. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Roy Zang 提交于
T4240 internal UTMI phy is different comparing to previous UTMI PHY in P3041. This patch adds USB 2.0 UTMI Dual PHY new memory map and enable it for T4240. The phy timing is very sensitive and moving the phy enable code to cpu_init.c will not work. Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 York Sun 提交于
T4240 has voltage ID fuse. Read the fuse and configure the voltage correctly. Core voltage has higher tolerance on over side than below. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 York Sun 提交于
Missing nodes of crypto, pme, etc in device tree is not a fatal error. Setting up the qman portal should skip the missing node and continue to finish the rest. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 York Sun 提交于
Should check if interleaving is enabled before using interleaving mode. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 York Sun 提交于
Update the timing table to support more rank density, based on the theory that similar density DIMMs have similar clock adjust and write level start timing. Update the timing for 1600 and 1866 MT/s. Tested with Micron MT18JSF1G72AZ-1G9E1 DIMMs, iDIMM M3CN-4GMJ3C0C-M92. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Roy Zang 提交于
Lane H on SerDes4 should be SATA2 instead of SATA1 Signed-off-by: NJerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Shaohui Xie 提交于
1. fix 10G mac offset by plus 8; 2. add second 10G port info for FM1 & FM2 when init ethernet info; 3. fix 10G lanes name to match lane protocol table; Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Shaohui Xie 提交于
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Roy Zang 提交于
Reverse the bit sequence to set and display serdes clock frequency correctly. The correct bit maps in BRDCFG2 are 0 1 2 3 4 5 6 7 S1RATE[1:0] S2RATE[1:0] S3RATE[1:0] S4RATE[1:0] Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Andy Fleming 提交于
The L1 D-cache on e6500 is write-through. This means that it's not considered a good idea to have the L1 up and running if the L2 is disabled. We don't actually *use* the L1 until after the L2 is brought up on e6500, so go ahead and move the L1 enablement after that code is done. Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Shaohui Xie 提交于
T4240QDS uses a SST instead of SPANSION SPI flash. Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 York Sun 提交于
Fix ccsr_gur for corenet platform. Remove non-exist registers. Add fuse status register. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Andy Fleming 提交于
Makes it a bit easier to see if we've properly set them. While we're in there, modify the accesses to HDBCR0 and HDBCR1 to actually use those definitions. Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Sandeep Singh 提交于
The bit positions for FMAN1 freq in RCW is different for B4860. Also addded a case when FMAN1 frewuency is equal to systembus. Signed-off-by: NSandeep Singh <Sandeep@freescale.com> Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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- 14 5月, 2013 20 次提交
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由 Simon Glass 提交于
Add selected coreboot timestamps into bootstage to get a unified view of the boot timings. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Coreboot provides a lot of useful timing information. Provide a facility to add this to bootstage on start-up. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
We don't use zlib and gzip but do use lzo, so enable this. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
This local variable is not used unless CONFIG_GZIP is defined. Fix it. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Add a function which allows a (file, function, line number) to be marked in bootstage. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NChe-Liang Chiou <clchiou@chromium.org>
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由 Simon Glass 提交于
This is a convenient way of finding out where boottime is going. Enable it for coreboot. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Doug Anderson 提交于
In a previous CL we added the bootstage_relocate(), which should be called after malloc is initted. Now we call it on generic board. Signed-off-by: NDoug Anderson <dianders@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Doug Anderson 提交于
Any pointers to name strings that were passed to bootstage_mark_name() pre-relocation should be copied post-relocation so that they don't get trashed as the original location of U-Boot is re-used for other purposes. This change introduces a new API call that should be called from board_init_r() after malloc has been initted on any board that uses bootstage. Signed-off-by: NDoug Anderson <dianders@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Some functions don't have a stub for when CONFIG_BOOTSTAGE is not defined. Add one to avoid #ifdefs in the code when this is used in U-Boot. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NChe-Liang Chiou <clchiou@chromium.org> Reviewed-by: NTom Wai-Hong Tam <waihong@chromium.org>
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由 Simon Glass 提交于
While we don't want PCAT timers for timing, we want timer 2 so that we can still make a beep. Re-purpose the PCAT driver for this, and enable it in coreboot. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
This is no longer used since we prefer the more accurate TSC timer, so remove the dead code. Signed-off-by: NSimon Glass <sjg@chromium.org> Acked-by: NGraeme Russ <graeme.russ@gmail.com>
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由 Simon Glass 提交于
Tidy up some old broken and unneeded implementations. These are not used by coreboot or anything else now. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NGabe Black <gabeblack@chromium.org> Reviewed-by: NMichael Spang <spang@chromium.org> Reviewed-by: NVadim Bendebury <vbendeb@chromium.org> Acked-by: NGraeme Russ <graeme.russ@gmail.com>
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由 Simon Glass 提交于
This timer runs at a rate that can be calculated, well over 100MHz. It is ideal for accurate timing and does not need interrupt servicing. Tidy up some old broken and unneeded implementations at the same time. To provide a consistent view of boot time, we use the same time base as coreboot. Use the base timestamp supplied by coreboot as U-Boot's base time. Signed-off-by: Simon Glass <sjg@chromium.org>base Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
The 'Starting linux' message appears twice in the code, but both call through the same place. Unify these and add calls to bootstage to mark the occasion. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NMichael Spang <spang@chromium.org> Acked-by: NGraeme Russ <graeme.russ@gmail.com>
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由 Simon Glass 提交于
panic_puts() can be called in early boot to display a message. It might help with early debugging. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NTom Wai-Hong Tam <waihong@chromium.org>
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由 Simon Glass 提交于
Several files use the global_data pointer without declaring it. This works because the declaration is currently a NOP. But still it is better to fix this so that x86 lines up with other archs. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Since we use CONFIG_SYS_GENERIC_BOARD on x86, we don't need this anymore. Signed-off-by: NSimon Glass <sjg@chromium.org> Acked-by: NGraeme Russ <graeme.russ@gmail.com>
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由 Simon Glass 提交于
Since we don't have real-mode code now, we can remove this chunk of the link script. Signed-off-by: NSimon Glass <sjg@chromium.org> Acked-by: NGraeme Russ <graeme.russ@gmail.com>
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由 Simon Glass 提交于
Graeme Russ pointed out that this code is no longer used. Remove it. Signed-off-by: NSimon Glass <sjg@chromium.org> Acked-by: NGraeme Russ <graeme.russ@gmail.com>
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- 13 5月, 2013 1 次提交
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由 Andreas Bießmann 提交于
Commit 18652864 (Introduce generic link section.h symbol files) changed the __bss_end symbol type from char[] to ulong. This led to wrong relocation parameters which ended up in a not working u-boot. Unfortunately this is not clear to see cause due to RAM aliasing we may get a 'half-working' u-boot then. Fix this by dereferencing the __bss_end symbol where needed. Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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