- 02 9月, 2021 1 次提交
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由 Chia-Wei Wang 提交于
A U-Boot image could be loaded and executed at a different location than it was linked at. For example, Aspeed takes a stable release version of U-Boot image as the golden one for recovery purposes. When the primary storage such as flash is corrupted, the golden image would be loaded to any SRAM/DRAM address on demands through ethernet/UART/etc and run for rescue. To deal with this condition, the PIE is needed as there is only one signed, golden image, which could be however executed at different places. This patch adds the PIE support for ARMv7 platform. Signed-off-by: NChia-Wei Wang <chiawei_wang@aspeedtech.com>
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- 01 9月, 2021 1 次提交
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由 Tom Rini 提交于
This converts the following to Kconfig: CONFIG_SKIP_LOWLEVEL_INIT CONFIG_SKIP_LOWLEVEL_INIT_ONLY In order to do this, we need to introduce SPL and TPL variants of these options so that we can clearly disable these options only in SPL in some cases, and both instances in other cases. Signed-off-by: NTom Rini <trini@konsulko.com>
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- 18 5月, 2019 1 次提交
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由 Trevor Woerner 提交于
While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: NAlexey Brodkin <abrodkin@synopsys.com> Signed-off-by: NTrevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: NTom Rini <trini@konsulko.com>
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- 27 11月, 2018 1 次提交
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由 Andrew F. Davis 提交于
Some erratum workarounds call into C code before the stack is setup, this can lead to values pushed onto the stack being lost, firewall exceptions, and other undefined behavior. Setup a temporary stack to allow these functions to work correctly. Signed-off-by: NAndrew F. Davis <afd@ti.com> Acked-by: NAndreas Dannenberg <dannenberg@ti.com> Reviewed-by: NNishanth Menon <nm@ti.com>
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- 29 6月, 2018 2 次提交
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由 Nishanth Menon 提交于
As recommended by Arm in [1], ACTLR[0] (Enable invalidates of BTB) needs to be set[2] for BTB to be invalidated on ICIALLU. This needs to be done unconditionally for Cortex-A15 processors. Provide a config option for platforms to enable this option based on impact analysis for products. NOTE: This patch in itself is NOT the final solution, this requires: a) Implementation of v7_arch_cp15_set_acr on SoCs which may not provide direct access to ACR register. b) Operating Systems such as Linux to provide adequate workaround in the right locations. c) This workaround applies to only the boot processor. It is important to apply workaround as necessary (context-save-restore) around low power context loss OR additional processors as necessary in either firmware support OR elsewhere in OS. [1] https://developer.arm.com/support/security-update [2] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0438c/BABGHIBG.html Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Tony Lindgren <tony@atomide.com> Cc: Robin Murphy <robin.murphy@arm.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Christoffer Dall <christoffer.dall@linaro.org> Cc: Andre Przywara <Andre.Przywara@arm.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Tom Rini <trini@konsulko.com> Cc: Michael Nazzareno Trimarchi <michael@amarulasolutions.com> Signed-off-by: NNishanth Menon <nm@ti.com> Tested-by: NFabio Estevam <fabio.estevam@nxp.com>
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由 Nishanth Menon 提交于
As recommended by Arm in [1], IBE[2] has to be enabled unconditionally for BPIALL to be functional on Cortex-A8 processors. Provide a config option for platforms to enable this option based on impact analysis for products. NOTE: This patch in itself is NOT the final solution, this requires: a) Implementation of v7_arch_cp15_set_acr on SoCs which may not provide direct access to ACR register. b) Operating Systems such as Linux to provide adequate workaround in the right locations. c) This workaround applies to only the boot processor. It is important to apply workaround as necessary (context-save-restore) around low power context loss OR additional processors as necessary in either firmware support OR elsewhere in OS. [1] https://developer.arm.com/support/security-update [2] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0344k/Bgbffjhh.html Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Tony Lindgren <tony@atomide.com> Cc: Robin Murphy <robin.murphy@arm.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Christoffer Dall <christoffer.dall@linaro.org> Cc: Andre Przywara <Andre.Przywara@arm.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Tom Rini <trini@konsulko.com> Cc: Michael Nazzareno Trimarchi <michael@amarulasolutions.com> Signed-off-by: NNishanth Menon <nm@ti.com> Tested-by: NFabio Estevam <fabio.estevam@nxp.com>
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- 08 5月, 2018 2 次提交
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由 Michal Simek 提交于
The Cortex-R* processors are a mid-range CPUs for use in deeply-embedded, real-time systems. It implements the ARMv7-R architecture, and includes Thumb-2 technology for optimum code density and processing throughput. Except for MPU(Memory Protection Unit) and few CP15 registers, most of the features are compatible with v7 architecture. So,reuse the same armv7 folder and introduce a new config CPU_V7R in order to differentiate from v7 based platforms. Tested-by: NMichal Simek <michal.simek@xilinx.com> Reviewed-by: NTom Rini <trini@konsulko.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Lokesh Vutla 提交于
Not all ARM V7 based cpus has VBAR for remapping vector base address. So, update VBAR only if it available. Reviewed-by: NTom Rini <trini@konsulko.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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- 07 5月, 2018 1 次提交
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由 Tom Rini 提交于
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: NTom Rini <trini@konsulko.com>
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- 10 1月, 2018 1 次提交
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由 Siarhei Siamashka 提交于
By applying this patch, we are ensuring that the code paths responsible for applying errata workarounds are also exercised on CPU revisions, which actually don't need these workarounds. Only CONFIG_ARM_ERRATA_621766, CONFIG_ARM_ERRATA_454179, CONFIG_ARM_ERRATA_725233 and CONFIG_ARM_ERRATA_430973 are covered by this patch (Cortex-A8). This improves code coverage when testing U-Boot builds on newer hardware. In particular, the problematic commit 00bbe96e ("arm: omap: Unify get_device_type() function") would break both BeageBoard and BeagleBoard XM rather than just older BeagleBoard. As an additional bonus, we need fewer instructins and the SPL size is reduced. Signed-off-by: NSiarhei Siamashka <siarhei.siamashka@gmail.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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- 22 11月, 2017 1 次提交
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由 Philipp Tomsich 提交于
As no '.type' was set for save_boot_params_ret in start.S, binutils did not track whether it was emitted as A32 or T32. By properly marking save_boot_params_ret as a potential function entry, we can make sure that the compiler will insert the appropriate instructions for branching to save_boot_params_ret both for call-sites emitted as A32 and T32. Reported-by: NAndy Yan <andy.yan@rock-chips.com> Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: NAndy Yan <andy.yan@rock-chips.com>
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- 16 8月, 2017 1 次提交
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由 Peng Fan 提交于
Under very rare timing circumstances, transitioning into streaming mode might create a data corruption. Present on Two or more processors or 1 core with ACP, all revisions. This erratum can be worked round by setting bit[22] of the undocumented Diagnostic Control Register to 1. Signed-off-by: NPeng Fan <peng.fan@nxp.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@konsulko.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: NStefano Babic <sbabic@denx.de>
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- 08 5月, 2017 1 次提交
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由 Nisal Menuka 提交于
ARM errata 852421 and 852423 applies to r1p0, r1p1 and r1p2 revisions of Cortex-A17 processors. These workarounds exist in Linux kernel and I thought it would be better to add them in to U-Boot. Signed-off-by: NNisal Menuka <nisalmenuka23@gmail.com>
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- 15 3月, 2017 1 次提交
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由 Siarhei Siamashka 提交于
The workaround for ARM errata 725233 had been lost since commit 45bf0585 (armv7: adapt omap3 to the new cache maintenance framework). Bring it back in order to avoid very difficult to reproduce, but actually encountered in the wild CPU deadlocks when running software rendered X11 desktop on OMAP3530 hardware. Signed-off-by: NSiarhei Siamashka <siarhei.siamashka@gmail.com> Reviewed-by: NTom Rini <trini@konsulko.com> [trini: Migrate to Kconfig] Signed-off-by: NTom Rini <trini@konsulko.com>
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- 07 10月, 2016 1 次提交
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由 Keerthy 提交于
On some of the SoCs one cannot enable hypervisor mode directly from the u-boot because the ROM code puts the chip to supervisor mode after it jumps to boot loader. Hence introduce a weak function which can be overridden based on the SoC type and switch to hypervisor mode in a custom way. Cc: beagleboard-x15@googlegroups.com Signed-off-by: NKeerthy <j-keerthy@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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- 13 6月, 2016 1 次提交
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由 Simon Glass 提交于
At present CONFIG_SKIP_LOWLEVEL_INIT prevents U-Boot from calling lowlevel_init(). This means that the instruction cache is not enabled and the board runs very slowly. What is really needed in many cases is to skip the call to lowlevel_init() but still perform CP15 init. Add an option to handle this. Reviewed-by: NHeiko Schocher <hs@denx.de> Tested-on: smartweb, corvus, taurus, axm Tested-by: NHeiko Schocher <hs@denx.de> Reviewed-by: NJoe Hershberger <joe.hershberger@ni.com> Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NAndreas Bießmann <andreas@biessmann.org>
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- 13 8月, 2015 1 次提交
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由 Nishanth Menon 提交于
Add workaround for Cortex-A15 ARM erratum 801819 which says in summary that "A livelock can occur in the L2 cache arbitration that might prevent a snoop from completing. Under certain conditions this can cause the system to deadlock. " Recommended workaround is as follows: Do both of the following: 1) Do not use the write-back no-allocate memory type. 2) Do not issue write-back cacheable stores at any time when the cache is disabled (SCTLR.C=0) and the MMU is enabled (SCTLR.M=1). Because it is implementation defined whether cacheable stores update the cache when the cache is disabled it is not expected that any portable code will execute cacheable stores when the cache is disabled. For implementations of Cortex-A15 configured without the “L2 arbitration register slice” option (typically one or two core systems), you must also do the following: 3) Disable write-streaming in each CPU by setting ACTLR[28:25] = 0b1111 So, we provide an option to disable write streaming on OMAP5 and DRA7. It is a rare condition to occur and may be enabled selectively based on platform acceptance of risk. Applies to: A15 revisions r2p0, r2p1, r2p2, r2p3 or r2p4 and REVIDR[3] is set to 0. Note: certain unicore SoCs *might* not have REVIDR[3] not set, but might not meet the condition for the erratum to occur when they donot have ACP (Accelerator Coherency Port) hooked to ACE (AXI Coherency Extensions). Such SoCs will need the work around handled in the SoC specific manner, since there is no ARM generic manner to detect such configurations. Based on ARM errata Document revision 18.0 (22 Nov 2013) Suggested-by: NRichard Woodruff <r-woodruff2@ti.com> Suggested-by: NBrad Griffis <bgriffis@ti.com> Reviewed-by: NBrad Griffis <bgriffis@ti.com> Signed-off-by: NNishanth Menon <nm@ti.com>
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- 07 7月, 2015 1 次提交
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由 Pavel Machek 提交于
Fix big/small letters in comment. Signed-off-by: NPavel Machek <pavel@denx.de> Tested-by: NMarek Vasut <marex@denx.de>
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- 24 3月, 2015 1 次提交
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由 Rob Herring 提交于
Various files are needlessly rebuilt every time due to the version and build time changing. As version.h is not actually needed, remove the include. Signed-off-by: NRob Herring <robh@kernel.org> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefano Babic <sbabic@denx.de> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Marek Vasut <marex@denx.de> Cc: Tom Warren <twarren@nvidia.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Macpaul Lin <macpaul@andestech.com> Cc: Wolfgang Denk <wd@denx.de> Cc: York Sun <yorksun@freescale.com> Cc: Stefan Roese <sr@denx.de> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Philippe Reynes <tremyfr@yahoo.fr> Cc: Eric Jarrige <eric.jarrige@armadeus.org> Cc: "David Müller" <d.mueller@elsoft.ch> Cc: Phil Edworthy <phil.edworthy@renesas.com> Cc: Robert Baldyga <r.baldyga@samsung.com> Cc: Torsten Koschorrek <koschorrek@synertronixx.de> Cc: Anatolij Gustschin <agust@denx.de> Reviewed-by: NLinus Walleij <linus.walleij@linaro.org> Reviewed-by: NŁukasz Majewski <l.majewski@samsung.com>
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- 13 3月, 2015 4 次提交
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由 Nishanth Menon 提交于
621766: Under a specific set of conditions, executing a sequence of NEON or vfp load instructions can cause processor deadlock Impacts: Every Cortex-A8 processors with revision lower than r2p1 Work around: Set L1NEON to 1 Based on ARM errata Document revision 20.0 (13 Nov 2010) Signed-off-by: NNishanth Menon <nm@ti.com> Tested-by: NMatt Porter <mporter@konsulko.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Nishanth Menon 提交于
430973: Stale prediction on replaced inter working branch causes Cortex-A8 to execute in the wrong ARM/Thumb state Impacts: Every Cortex-A8 processors with revision lower than r2p1 Work around: Set IBE to 1 Based on ARM errata Document revision 20.0 (13 Nov 2010) Signed-off-by: NNishanth Menon <nm@ti.com> Tested-by: NMatt Porter <mporter@konsulko.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Nishanth Menon 提交于
454179: Stale prediction may inhibit target address misprediction on next predicted taken branch Impacts: Every Cortex-A8 processors with revision lower than r2p1 Work around: Set IBE and disable branch size mispredict to 1 Also provide a hook for SoC specific handling to take place if needed. Based on ARM errata Document revision 20.0 (13 Nov 2010) Signed-off-by: NNishanth Menon <nm@ti.com> Tested-by: NMatt Porter <mporter@konsulko.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Nishanth Menon 提交于
Add workaround for Cortex-A15 ARM erratum 798870 which says "If back-to-back speculative cache line fills (fill A and fill B) are issued from the L1 data cache of a CPU to the L2 cache, the second request (fill B) is then cancelled, and the second request would have detected a hazard against a recent write or eviction (write B) to the same cache line as fill B then the L2 logic might deadlock." Implementations for SoC families such as Exynos, OMAP5/DRA7 etc will be widely different. Every SoC has slightly different manner of setting up access to L2ACLR and similar registers since the Secure Monitor handling of Secure Monitor Call(smc) is diverse. Hence an weak function is introduced which may be overriden to implement SoC specific accessor implementation. Based on ARM errata Document revision 18.0 (22 Nov 2013) Signed-off-by: NNishanth Menon <nm@ti.com> Tested-by: NMatt Porter <mporter@konsulko.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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- 17 2月, 2015 3 次提交
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由 Siarhei Siamashka 提交于
So that the CONFIG_SPL_FEL option is not needed anymore. And the regular SPL binary, generated by the default u-boot build, is now also bootable over USB in the FEL mode. The SPL still can boot from the SD card too. A bunch of system registers need to be saved/restored in order to ensure that the IRQ handler still works in the BROM FEL code after getting control back from the SPL. This is done in the sunxi code instead of abusing ifdefs in 'start.S'. The decision whether to load the main u-boot binary from the SD card or return to the FEL code in the BROM is done at runtime. Signed-off-by: NSiarhei Siamashka <siarhei.siamashka@gmail.com> [hdegoede@redhat.com: Since we now restore various regs before returning to the FEL BROM code we can drop the sunxi specific #ifdefs in start.S] Acked-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 Simon Glass 提交于
Make sunxi's FEL code fit with the normal U-Boot boot sequence instead of creating its own. There are some #ifdefs required in start.S. Future work will hopefully remove these. This series is available at u-boot-dm, branch sunxi-working. Signed-off-by: NSimon Glass <sjg@chromium.org> Acked-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 Simon Glass 提交于
The link register value can be required on some boards (e.g. FEL mode on sunxi) so use a branch instruction to jump to save_boot_params() instead of a branch link. This requires a branch back to save_boot_params_ret so adjust the users to deal with this. For exynos just drop the function since it doesn't do anything. Signed-off-by: NSimon Glass <sjg@chromium.org> Acked-by: NSiarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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- 30 1月, 2015 1 次提交
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由 Peng Fan 提交于
SCTLR is the abbreviation of System Control Register, so we should use SCTLR but not SCTRL. Signed-off-by: NPeng Fan <Peng.Fan@freescale.com>
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- 29 10月, 2014 1 次提交
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由 Georges Savoundararadj 提交于
This commit relocates the exception vectors. As ARM1176 and ARMv7 have the security extensions, it uses VBAR. For the other ARM processors, it copies the relocated exception vectors to the correct address: 0x00000000 or 0xFFFF0000. Signed-off-by: NGeorges Savoundararadj <savoundg@gmail.com> Acked-by: NAlbert ARIBAUD <albert.u.boot@aribaud.net> Cc: Tom Warren <twarren@nvidia.com>
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- 15 5月, 2014 2 次提交
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由 Albert ARIBAUD 提交于
Exception handling is basically identical for all ARM targets. Factorize it out of the various start.S files and into a single vectors.S file, and adjust linker scripts accordingly. Signed-off-by: NAlbert ARIBAUD <albert.u.boot@aribaud.net>
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由 Albert ARIBAUD 提交于
Signed-off-by: NAlbert ARIBAUD <albert.u.boot@aribaud.net>
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- 08 4月, 2014 2 次提交
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由 Nitin Garg 提交于
Full cache line writes to the same memory region from at least two processors might deadlock the processor. Exists on r1, r2, r3 revisions. Signed-off-by: NNitin Garg <nitin.garg@freescale.com> Acked-by: NFabio Estevam <fabio.estevam@freescale.com>
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由 Nitin Garg 提交于
A short loop including a DMB instruction might cause a denial of service on another processor which executes a CP15 broadcast operation. Exists on r1, r2, r3, r4 revisions. Signed-off-by: NNitin Garg <nitin.garg@freescale.com> Acked-by: NDirk Behme <dirk.behme@de.bosch.com>
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- 27 2月, 2014 1 次提交
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由 Albert ARIBAUD 提交于
Remove the last uses of symbol offsets in ARM U-Boot. Remove some needless uses of _TEXT_BASE. Remove all _TEXT_BASE definitions. Signed-off-by: NAlbert ARIBAUD <albert.u.boot@aribaud.net>
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- 26 1月, 2014 1 次提交
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由 Marek Vasut 提交于
Make indirect vectors addresses global, so they can be replaced by various code that needs to do so. For example the MX6 PCI express driver needs to temporarily replace data abort handler when reading the config space. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
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- 15 10月, 2013 1 次提交
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由 Wolfgang Denk 提交于
Signed-off-by: NWolfgang Denk <wd@denx.de>
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- 24 7月, 2013 1 次提交
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由 Wolfgang Denk 提交于
Signed-off-by: NWolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: NTom Rini <trini@ti.com>
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- 31 5月, 2013 2 次提交
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由 Albert ARIBAUD 提交于
Replace all relocate_code routines from ARM start.S files with a single instance in file arch/arm/lib/relocate.S. For PXA, this requires moving the dcache unlocking code from within relocate_code into c_runtime_cpu_setup. Signed-off-by: NAlbert ARIBAUD <albert.u.boot@aribaud.net> Reviewed-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com> Tested-by: NSimon Glass <sjg@chromium.org>
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由 Albert ARIBAUD 提交于
Signed-off-by: NAlbert ARIBAUD <albert.u.boot@aribaud.net> Reviewed-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com> Tested-by: NSimon Glass <sjg@chromium.org>
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- 16 4月, 2013 2 次提交
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由 Tom Warren 提交于
A start vector fix was added by AneeshV for OMAP4 (commit 0d479b53), and caused the old monilithic Tegra builds to hang due to an undefined instruction trap. Previously, the code needed to run on both the AVP (ARM7TDI) and A9, and the AVP doesn't have a CP15 register. I corrected this in commit 6d6c0bae w/#ifndef CONFIG_TEGRA, but now that we use SPL, and boot the AVP w/o any ARMv7 code, I can revert my change, and make Aneesh's change apply to Tegra. Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Andre Przywara 提交于
The KVM and Xen hypervisors for the Cortex-A15 virtualization implementation need to be entered in HYP mode. Should the primary board firmware already enter HYP mode (Calxeda firmware does that), we should not deliberately drop back to SVC mode. Since U-boot does not use the MMU, running in HYP mode is just fine. Signed-off-by: NAndre Przywara <andre.przywara@linaro.org>
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