- 09 1月, 2008 4 次提交
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由 Stefan Roese 提交于
On LWMON5 we now use d-cache as init-ram and stack. The SPR POST test uses self modifying code and this doesn't work with stack in d-cache, since I can't move the code from d-cache to i-cache. We move the SPR test to be executed a little later, after relocation. Then stack is located in SDRAM and this self-modifying code is no problem anymore. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
This patch configures the LWMON5 port to use d-cache as init-ram and the unused GPT0_COMP6 as POST WORD storage. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
The privious 4xx POST implementation only supported storing the POST WORD in OCM. Since we need to reserve the OCM on LWMON5 for the logbuffer we need to store the POST WORD in some other non volatile location. This patch adds CFG_POST_ALT_WORD_ADDR to specify an address for such a location. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
This patch adds support for locking the init-ram/stack in d-cache, so that other regions may use d-cache as well Note, that this current implementation locks exactly 4k of d-cache, so please make sure that you don't define a bigger init-ram area. Take a look at the lwmon5 440EPx implementation as a reference. Signed-off-by: NStefan Roese <sr@denx.de>
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- 29 12月, 2007 8 次提交
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由 Stefan Roese 提交于
Conflicts: cpu/ppc4xx/fdt.c include/configs/kilauea.h include/configs/sequoia.h Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Signed-off-by: NStefan Roese <sr@denx.de>
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由 Matthias Fuchs 提交于
This patch brings the PMC440 board configuration file. Finally it enables the PMC440 board support. Signed-off-by: NMatthias Fuchs <matthias.fuchs@esd-electronics.com>
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由 Matthias Fuchs 提交于
This patch adds some BSP commands and FPGA booting support for esd's PMC440 boards. Signed-off-by: NMatthias Fuchs <matthias.fuchs@esd-electronics.com>
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由 Matthias Fuchs 提交于
This patch adds the first files for the new esd PMC440 boards. The next two patches will complete the PMC440 board support. Signed-off-by: NMatthias Fuchs <matthias.fuchs@esd-electronics.com>
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由 Matthias Fuchs 提交于
- add EEPROM write protection for esd PLU405 boards. - initialize NAND GPIOs - use correct io accessors - cleanup Signed-off-by: NMatthias Fuchs <matthias.fuchs@esd-electronics.com>
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由 Matthias Fuchs 提交于
This patch fixes esd's LCD dectection code to work correctly with newer gcc versions. Signed-off-by: NMatthias Fuchs <matthias.fuchs@esd-electronics.com>
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由 Matthias Fuchs 提交于
- add EEPROM write protection - initialize NAND GPIOs - use correct io accessors - slow down I2C clock to 100kHz - enable ext. I2C bus - cleanup Signed-off-by: NMatthias Fuchs <matthias.fuchs@esd-electronics.com>
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- 28 12月, 2007 28 次提交
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由 Stefan Roese 提交于
In an attmemt to clean up the 4xx start.S file, I removed the enabling of the internal 405EP PCI arbiter. This is needed for multiple other 405EP platforms, like most of the esd 405EP. Now the internal PCI arbiter is enabled again per default as it has been before. Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NMatthias Fuchs <matthias.fuchs@esd-electronics.com>
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由 Stefan Roese 提交于
Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NMatthias Fuchs <matthias.fuchs@esd-electronics.com>
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由 Stefan Roese 提交于
Use correct link to nand_ecc now located in drivers/mtd/nand/ for the platforms mentioned above. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
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由 Matthias Fuchs 提交于
This board never left prototyping state and it became a millstone round my neck. So remove it. Signed-off-by: NMatthias Fuchs <matthias.fuchs@esd-electronics.com>
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由 Larry Johnson 提交于
These patches add support for the PPC440EPx-based "Korat" board to U-Boot. They are based primarily on support for the Sequoia board. Signed-off-by: NLarry Johnson <lrj@acm.org>
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由 Larry Johnson 提交于
This patch supplies the configuration file for the Korat PPC440EPx- processor board. Signed-off-by: NLarry Johnson <lrj@acm.org>
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由 Larry Johnson 提交于
Signed-off-by: NLarry Johnson <lrj@acm.org>
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由 Larry Johnson 提交于
This patch adds SPD DDR2 support for the 440EPx ("Denali") SDRAM controller. It should also work on the 440GRx. It is based on the DDR2 SPD code for the 440EP/440EPx, but makes no provision for DDR1 support. This code has been tested on prototype Korat boards with three Kingston DIMMS: 512 MiB ECC (one rank), 512 MiB non-ECC (one rank) and 1 GiB ECC (two ranks). The Korat board has a single DIMM socket, but support has been provided (though not tested) for boards with two DIMM sockets. Signed-off-by: NLarry Johnson <lrj@acm.org>
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由 Larry Johnson 提交于
This patch creates a non-board-specific file for performing the SDRAM data-eye search. It also adds ECC error checking to the test of valid data on readback when ECC is enabled. Signed-off-by: NLarry Johnson <lrj@acm.org>
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由 Larry Johnson 提交于
This patch adds the Denali SDRAM controller definitions to "ppc440.h". It also fixes two typos in the definitions, so the board-specific "sdram.h" files containing these definitions are also fixed to avoid compiler warnings. Signed-off-by: NLarry Johnson <lrj@acm.org>
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由 Larry Johnson 提交于
This patch adds a new switch: "CONFIG_PHY_DYNAMIC_ANEG". When this symbol is defined, the PHY will advertise it's capabilities for autonegotiation based on the capabilities shown in the PHY's status registers, including 1000BASE-X. When "CONFIG_PHY_DYNAMIC_ANEG" is not defined, the PHY will advertise hard-coded capabilities, as before. Signed-off-by: NLarry Johnson <lrj@acm.org>
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由 Larry Johnson 提交于
This driver is based on the driver for the LM75. Signed-off-by: NLarry Johnson <lrj@acm.org>
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由 Larry Johnson 提交于
This driver is based on the driver for the M41T11. In the intended application, the RTC will be powered by a large capacitor, rather than a battery. The driver therefore checks to see whether the RTC has lost power. The chip's OUT bit is normally reset from its power-up state. If the OUT bit is read as set, or if the date and time are not valid, then the RTC is assumed to have lost power, and its date and time are reset to 1900-01-01 00:00:00. Support for adjusting the speed of the clock to improve accuracy is provided through an environment variable. Signed-off-by: NLarry Johnson <lrj@acm.org>
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由 Larry Johnson 提交于
Signed-off-by: NLarry Johnson <lrj@acm.org>
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由 Larry Johnson 提交于
Signed-off-by: NLarry Johnson <lrj@acm.org>
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由 Larry Johnson 提交于
Signed-off-by: NLarry Johnson <lrj@acm.org>
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由 Stefan Roese 提交于
Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
On Sequoia & LWMON5 the virtual address of the POST cache test is now moved to a bigger address. This enables usage of more memory on those boards. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
As repoted by Larry Johnson, running "diag run cache" caused a crash in U-Boot. This problem was introduced by a patch that removed the TLB entry for the cache test after the test has completed. Since this TLB was only setup once, a 2nd attempt to run this cache test failed with a crash. Now this TLB entry is created every time the routine is called. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Now the cpu node setup ("timebase-frequency" and "clock-frequency") is without using the absolute path to the cpu node. This makes it possible to use this U-Boot version with both versions of cpu-node naming "cpu@0" and the former "PowerPC,440EPx@0". Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Now that the 440EPx ECC test is not board specific anymore remove this Makefile. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Anatolij Gustschin 提交于
ppc4xx clear_bss() fails if BSS segment size is not divisible by 4 without remainder. This patch provides fix for this problem. Signed-off-by: NAnatolij Gustschin <agust@denx.de>
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由 Niklaus Giger 提交于
Signed-off-by: NNiklaus Giger <niklaus.giger@netstal.com>
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由 Markus Klotzbücher 提交于
When using dhcp/bootp the "netmask" environment variable is not set because CONFIG_BOOTP_SUBNETMASK is not defined. But usually this is desireable, so the following patch adds this this option to the board config. Signed-off-by: NMarkus Klotzbuecher <mk@denx.de> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Larry Johnson 提交于
This patch allows the ECC POST to be used for different boards with the PPC440 Denali SDRAM controller. Modifications include skipping the test if ECC is not enabled (as for non-ECC DIMMs) and adding synchronization to prevent timing errors. Signed-off-by: NLarry Johnson <lrj@acm.org>
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