- 20 10月, 2020 10 次提交
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由 Lad Prabhakar 提交于
Sync the R8A77990 SoC PFC tables with Linux 5.9 , commit bbf5c979011a. Signed-off-by: NLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: NBiju Das <biju.das.jz@bp.renesas.com>
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由 Lad Prabhakar 提交于
Import RZ/G2E (R8A774C0) clock tables from Linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: NLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: NBiju Das <biju.das.jz@bp.renesas.com>
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由 Biju Das 提交于
This sync's the RZ/G2H clock tables with mainline linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: NBiju Das <biju.das.jz@bp.renesas.com> Reviewed-by: NLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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由 Biju Das 提交于
This sync's the RZ/G2N clock tables with mainline linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: NBiju Das <biju.das.jz@bp.renesas.com> Reviewed-by: NLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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由 Lad Prabhakar 提交于
Import R8A774C0 (RZ/G2E) SoC DTSI and headers from Linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: NLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: NBiju Das <biju.das.jz@bp.renesas.com>
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由 Lad Prabhakar 提交于
Add config support for RZ/G2E (a.k.a R8A774C0) SoC. Signed-off-by: NLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: NBiju Das <biju.das.jz@bp.renesas.com>
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由 Biju Das 提交于
Add config support for RZ/G2H(a.k.a R8A774E1) SoC. Signed-off-by: NBiju Das <biju.das.jz@bp.renesas.com> Reviewed-by: NLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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由 Biju Das 提交于
Add config support for RZ/G2N(a.k.a R8A774B1) SoC. Also fixed the alignment issue on R8A774A1 config. Signed-off-by: NBiju Das <biju.das.jz@bp.renesas.com> Reviewed-by: NLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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由 Biju Das 提交于
Add RPC entry into the R8A774A1 clock driver tables. Signed-off-by: NBiju Das <biju.das.jz@bp.renesas.com> Reviewed-by: NLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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由 Biju Das 提交于
Add fallback compatibility string for R-Car Gen3 and RZ/G2. Also sorted the compatible string as per SoC ID. Signed-off-by: NBiju Das <biju.das.jz@bp.renesas.com>
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- 19 10月, 2020 13 次提交
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https://gitlab.denx.de/u-boot/custodians/u-boot-atmel由 Tom Rini 提交于
Second set of u-boot-atmel features for 2021.01 cycle: This feature set brings the rework of the clock tree for sam9x60 SoC. This makes the clock tree fully compatible with Common Clock Framework and allows full clock configuration in U-Boot. This means that the sam9x60 boards can boot now using U-Boot. This also includes the definitions for sam9x60 SiPs and a divisor fix for the clock on sama7g5 SoC.
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由 Eugen Hristev 提交于
This SoC has the 5th divisor for the mck0 master clock. Adapt the characteristics accordingly. Reported-by: NMihai Sain <mihai.sain@microchip.com> Signed-off-by: NEugen Hristev <eugen.hristev@microchip.com> Reviewed-by: NClaudiu Beznea <claudiu.beznea@microchip.com>
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由 Eugen Hristev 提交于
clk-master can have 5 divisors with a field width of 3 bits on some products. Change the mask and number of divisors accordingly. Reported-by: NMihai Sain <mihai.sain@microchip.com> Signed-off-by: NEugen Hristev <eugen.hristev@microchip.com> Reviewed-by: NClaudiu Beznea <claudiu.beznea@microchip.com>
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由 Nicolas Ferre 提交于
SAM9X60 SiP (System in Package) are added for SoC identification. Signed-off-by: NNicolas Ferre <nicolas.ferre@microchip.com>
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由 Claudiu Beznea 提交于
Use alphabetical order for entries in sam9x60ek-u-boot.dtsi Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>
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由 Claudiu Beznea 提交于
Update defconfigs for using common clock framework compatible clocks. Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>
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由 Claudiu Beznea 提交于
Use CCF compatible for PMC. With this, the board/SoC will be able to boot. Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>
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由 Claudiu Beznea 提交于
Use slow clock CCF compatible DT bindings. This will not break the above functionality as the SoC is not booting with current PMC bindings. Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>
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由 Claudiu Beznea 提交于
Use u-boot,dm-pre-reloc for slow xtal and main xtal. Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>
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由 Claudiu Beznea 提交于
Slow Xtal and Main Xtal are board specific. Add their proper frequency to board file. Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>
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由 Claudiu Beznea 提交于
Add SAM9X60 clock support compatible with CCF. Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>
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由 Claudiu Beznea 提交于
Heap base address is computed based on SYS_INIT_SP_ADDR by subtracting the SYS_MALLOC_F_LEN value in board_init_f_init_reserve(). Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>
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https://gitlab.denx.de/u-boot/custodians/u-boot-video由 Tom Rini 提交于
- add dw-mipi-dsi phy timings and Tx escape clock configuration - fix pwm backlight duty cycle calculation - migrate CONFIG_VIDEO_BMP_* and CONFIG_BMP_* to Kconfig
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- 18 10月, 2020 7 次提交
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由 Patrick Delaunay 提交于
Done with: ./tools/moveconfig.py BMP_16BPP BMP_24BPP BMP_32BPP Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Patrick Delaunay 提交于
Done with: ./tools/moveconfig.py VIDEO_BMP_RLE8 Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Patrick Delaunay 提交于
Done with: ./tools/moveconfig.py VIDEO_BMP_GZIP The 3 suspicious migration because CMD_BMP and SPLASH_SCREEN are not activated in these defconfigs: - trats_defconfig - s5pc210_universal_defconfig - trats2_defconfig Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Dario Binacchi 提交于
For levels equal to the maximum value, the duty cycle must be equal to the period. Signed-off-by: NDario Binacchi <dariobin@libero.it> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Dario Binacchi 提交于
The description of the 'max_level' field was incorrectly assigned to the 'min_level' field. Signed-off-by: NDario Binacchi <dariobin@libero.it>
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由 Neil Armstrong 提交于
The Amlogic D-PHY in the Amlogic AXG SoC Family does support a frequency higher than 10MHz for the TX Escape Clock, thus make the target rate configurable. This is based on the Linux commit [1] and adapted to the U-Boot driver. [1] a328ca7e4af3 ("drm/bridge: dw-mipi-dsi: permit configuring the escape clock rate") Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
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由 Neil Armstrong 提交于
The timing values for dw-dsi are often dependent on the used display and according to Philippe Cornu will most likely also depend on the used phy technology in the soc-specific implementation. To solve this and allow specific implementations to define them as needed add a new get_timing callback to phy_ops and call this from the dphy_timing function to retrieve the necessary values for the specific mode. This is based on the Linux commit [1] and adapted to the U-Boot driver. [1] 25ed8aeb9c39 ("drm/bridge/synopsys: dsi: driver-specific configuration of phy timings") Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
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- 17 10月, 2020 1 次提交
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由 Sean Anderson 提交于
syslog_test.h is in test/log/, not include/ Fixes: 52d3df7f ("log: Allow LOG_DEBUG to always enable log output") Signed-off-by: NSean Anderson <seanga2@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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- 16 10月, 2020 9 次提交
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https://gitlab.denx.de/u-boot/custodians/u-boot-marvell由 Tom Rini 提交于
- Fix Octeon SPI driver for Octeon TX2 - Fix and enhance Octeon watchdog driver - Misc minor enhancements to Octeon TX/TX2
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由 Tom Rini 提交于
- Bring in the next round of dev_xxx cleanup patches.
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由 Sean Anderson 提交于
Now that linux/compat.h does not define these macros, we do not need to undefine them. Signed-off-by: NSean Anderson <seanga2@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Sean Anderson 提交于
All users of these functions now include dm/device_compat.h directly. Signed-off-by: NSean Anderson <seanga2@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Tom Rini 提交于
Necessary for dev_xxx. Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Tom Rini 提交于
Necessary for dev_xxx. Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Tom Rini 提交于
Necessary for dev_xxx. Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Sean Anderson 提交于
This driver doesn't use DM (in the correct places), so we use a device and not a udevice. We also need to include device_compat.h Signed-off-by: NSean Anderson <seanga2@gmail.com>
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由 Sean Anderson 提交于
This was included, but was ifdef'd out. We also need dm.h for struct udevice. Signed-off-by: NSean Anderson <seanga2@gmail.com>
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