1. 10 8月, 2017 1 次提交
  2. 09 8月, 2017 1 次提交
  3. 01 8月, 2017 1 次提交
  4. 31 7月, 2017 1 次提交
  5. 26 7月, 2017 1 次提交
    • S
      Convert CONFIG_ENV_IS_IN_MMC/NAND/UBI and NOWHERE to Kconfig · 2be29653
      Simon Glass 提交于
      This converts the following to Kconfig:
         CONFIG_ENV_IS_IN_MMC
         CONFIG_ENV_IS_IN_NAND
         CONFIG_ENV_IS_IN_UBI
         CONFIG_ENV_IS_NOWHERE
      
      In fact this already exists for sunxi as a 'choice' config. However not
      all the choices are available in Kconfig yet so we cannot use that. It
      would lead to more than one option being set.
      
      In addition, one purpose of this series is to allow the environment to be
      stored in more than one place. So the existing choice is converted to a
      normal config allowing each option to be set independently.
      
      There are not many opportunities for Kconfig updates to reduce the size of
      this patch. This was tested with
      
         ./tools/moveconfig.py -i CONFIG_ENV_IS_IN_MMC
      
      And then manual updates.  This is because for CHAIN_OF_TRUST boards they
      can only have ENV_IS_NOWHERE set, so we enforce that via Kconfig logic
      now.
      Signed-off-by: NSimon Glass <sjg@chromium.org>
      Signed-off-by: NTom Rini <trini@konsulko.com>
      2be29653
  6. 25 7月, 2017 1 次提交
  7. 15 5月, 2017 1 次提交
    • T
      omap3: Migrate CONFIG_OMAP3_GPIO_X to Kconfig · 68ccab51
      Tom Rini 提交于
      The symbols CONFIG_OMAP3_GPIO_X control if we enable the clocks for a
      given GPIO bank in U-Boot.  select the required banks for each target.
      In some cases we need to also migrate from CONFIG_USB_EHCI (deprecated,
      in include/configs/) to CONFIG_USB_EHCI_HCD as we only require the GPIO
      bank to be enabled if USB is also enabled.
      Signed-off-by: NTom Rini <trini@konsulko.com>
      68ccab51
  8. 10 5月, 2017 1 次提交
    • A
      omap3_logic: Add Device Tree Support and more DM drivers · 15fde737
      Adam Ford 提交于
      This patch also removes all the excessive code for NS16550 intiailization
      as the device tree can do that now.  This also adds DM_I2C and DM_MMC
      since the overlying drivers have the built-in support already.  The
      corresponding include/config/omap3_logic.h also reduced in size
      due to the new device tree support.
      Signed-off-by: NAdam Ford <aford173@gmail.com>
      
      Changes in V2:
        Retain Auto-detect ability between SOM-LV and Torpedo
        Split this off from the device sub submissions
      15fde737
  9. 22 1月, 2017 1 次提交
  10. 20 1月, 2017 1 次提交
    • A
      ARM: omap3_logic: Refactor Boot Environmental variables · 476e16e8
      Adam Ford 提交于
      Some scripts are calling the same functions, so these changes consolidate
      common scripts together to reduce redundancy and shrink size a bit.  This
      also keeps the 'bootargs' variable from growing if manually called more
      than one time. This also adds NAND booting scripts based on newly consolidated
      scripts.
      Signed-off-by: NAdam Ford <aford173@gmail.com>
      476e16e8
  11. 15 1月, 2017 1 次提交
  12. 03 1月, 2017 2 次提交
  13. 22 11月, 2016 2 次提交
  14. 31 10月, 2016 2 次提交
  15. 12 10月, 2016 2 次提交
  16. 27 9月, 2016 1 次提交
  17. 07 9月, 2016 1 次提交
    • T
      TI: Rework SRAM definitions and maximums · fa2f81b0
      Tom Rini 提交于
      On all TI platforms the ROM defines a "downloaded image" area at or near
      the start of SRAM which is followed by a reserved area.  As it is at
      best bad form and at worst possibly harmful in corner cases to write in
      this reserved area, we stop doing that by adding in the define
      NON_SECURE_SRAM_IMG_END to say where the end of the downloaded image
      area is and make SRAM_SCRATCH_SPACE_ADDR be one kilobyte before this.
      At current we define the end of scratch space at 0x228 bytes past the
      start of scratch space this this gives us a lot of room to grow.  As
      these scratch uses are non-optional today, all targets are modified to
      respect this boundary.
      
      Tested on OMAP4 Pandaboard, OMAP3 Beagle xM
      
      Cc: Albert Aribaud <albert.u.boot@aribaud.net>
      Cc: Nagendra T S <nagendra@mistralsolutions.com>
      Cc: Vaibhav Hiremath <hvaibhav@ti.com>
      Cc: Lokesh Vutla <lokeshvutla@ti.com>
      Cc: Felipe Balbi <balbi@ti.com>
      Cc: Igor Grinberg <grinberg@compulab.co.il>
      Cc: Nikita Kiryanov <nikita@compulab.co.il>
      Cc: Paul Kocialkowski <contact@paulk.fr>
      Cc: Enric Balletbo i Serra <eballetbo@gmail.com>
      Cc: Adam Ford <aford173@gmail.com>
      Cc: Steve Sakoman <sakoman@gmail.com>
      Cc: Stefan Roese <sr@denx.de>
      Cc: Thomas Weber <weber@corscience.de>
      Cc: Hannes Schmelzer <oe5hpm@oevsv.at>
      Cc: Thomas Chou <thomas@wytron.com.tw>
      Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
      Cc: Simon Glass <sjg@chromium.org>
      Cc: Joe Hershberger <joe.hershberger@ni.com>
      Cc: Sam Protsenko <semen.protsenko@linaro.org>
      Cc: Heiko Schocher <hs@denx.de>
      Cc: Samuel Egli <samuel.egli@siemens.com>
      Cc: Michal Simek <michal.simek@xilinx.com>
      Cc: Wolfgang Denk <wd@denx.de>
      Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
      Cc: Ben Whitten <ben.whitten@gmail.com>
      Cc: Stefano Babic <sbabic@denx.de>
      Cc: Bin Meng <bmeng.cn@gmail.com>
      Cc: Sekhar Nori <nsekhar@ti.com>
      Cc: Mugunthan V N <mugunthanvnm@ti.com>
      Cc: "B, Ravi" <ravibabu@ti.com>
      Cc: "Matwey V. Kornilov" <matwey.kornilov@gmail.com>
      Cc: Ladislav Michl <ladis@linux-mips.org>
      Cc: Ash Charles <ashcharles@gmail.com>
      Cc: "Kipisz, Steven" <s-kipisz2@ti.com>
      Cc: Daniel Allred <d-allred@ti.com>
      Signed-off-by: NTom Rini <trini@konsulko.com>
      Tested-by: NLokesh Vutla <lokeshvutla@ti.com>
      Acked-by: NLokesh Vutla <lokeshvutla@ti.com>
      Tested-by: NLadislav Michl <ladis@linux-mips.org>
      fa2f81b0
  18. 27 8月, 2016 1 次提交
    • T
      ARM: Move SYS_CACHELINE_SIZE over to Kconfig · 067716ba
      Tom Rini 提交于
      This series moves the CONFIG_SYS_CACHELINE_SIZE.  First, in nearly all
      cases we are mirroring the values used by the Linux Kernel here.  Also,
      so long as (and in this case, it is true) we implement flushes in hunks
      that are no larger than the smallest implementation (and given that we
      mirror the Linux Kernel, again we are fine) it is OK to align higher.
      The biggest changes here are that we always use 64 bytes for CPU_V7 even
      if for example the underlying core is only 32 bytes (this mirrors
      Linux).  Second, we say ARM64 uses 64 bytes not 128 (as found in the
      Linux Kernel) as we do not need multi-platform support (to this degree)
      and only the Cavium ThunderX 88xx series has a use for such large
      alignment.
      
      Cc: Albert Aribaud <albert.u.boot@aribaud.net>
      Cc: Marek Vasut <marex@denx.de>
      Cc: Stefano Babic <sbabic@denx.de>
      Cc: Prafulla Wadaskar <prafulla@marvell.com>
      Cc: Luka Perkov <luka.perkov@sartura.hr>
      Cc: Stefan Roese <sr@denx.de>
      Cc: Nagendra T S <nagendra@mistralsolutions.com>
      Cc: Vaibhav Hiremath <hvaibhav@ti.com>
      Acked-by: NLokesh Vutla <lokeshvutla@ti.com>
      Cc: Steve Rae <steve.rae@raedomain.com>
      Cc: Igor Grinberg <grinberg@compulab.co.il>
      Cc: Nikita Kiryanov <nikita@compulab.co.il>
      Cc: Stefan Agner <stefan.agner@toradex.com>
      Acked-by: NHeiko Schocher <hs@denx.de>
      Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
      Cc: Peter Griffin <peter.griffin@linaro.org>
      Acked-by: NPaul Kocialkowski <contact@paulk.fr>
      Cc: Anatolij Gustschin <agust@denx.de>
      Acked-by: N"Pali Rohár" <pali.rohar@gmail.com>
      Cc: Adam Ford <aford173@gmail.com>
      Cc: Steve Sakoman <sakoman@gmail.com>
      Cc: Grazvydas Ignotas <notasas@gmail.com>
      Cc: Nishanth Menon <nm@ti.com>
      Cc: Stephen Warren <swarren@wwwdotorg.org>
      Cc: Robert Baldyga <r.baldyga@samsung.com>
      Cc: Minkyu Kang <mk7.kang@samsung.com>
      Cc: Thomas Weber <weber@corscience.de>
      Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
      Cc: David Feng <fenghua@phytium.com.cn>
      Cc: Alison Wang <b18965@freescale.com>
      Cc: Michal Simek <michal.simek@xilinx.com>
      Cc: Simon Glass <sjg@chromium.org>
      Cc: York Sun <york.sun@nxp.com>
      Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com>
      Cc: Mingkai Hu <mingkai.hu@nxp.com>
      Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
      Cc: Aneesh Bansal <aneesh.bansal@freescale.com>
      Cc: Saksham Jain <saksham.jain@nxp.com>
      Cc: Qianyu Gong <qianyu.gong@nxp.com>
      Cc: Wang Dongsheng <dongsheng.wang@nxp.com>
      Cc: Alex Porosanu <alexandru.porosanu@freescale.com>
      Cc: Hongbo Zhang <hongbo.zhang@nxp.com>
      Cc: tang yuantian <Yuantian.Tang@freescale.com>
      Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com>
      Cc: Josh Wu <josh.wu@atmel.com>
      Cc: Bo Shen <voice.shen@atmel.com>
      Cc: Viresh Kumar <viresh.kumar@linaro.org>
      Cc: Hannes Schmelzer <oe5hpm@oevsv.at>
      Cc: Thomas Chou <thomas@wytron.com.tw>
      Cc: Joe Hershberger <joe.hershberger@ni.com>
      Cc: Sam Protsenko <semen.protsenko@linaro.org>
      Cc: Bin Meng <bmeng.cn@gmail.com>
      Cc: Christophe Ricard <christophe-h.ricard@st.com>
      Cc: Anand Moon <linux.amoon@gmail.com>
      Cc: Beniamino Galvani <b.galvani@gmail.com>
      Cc: Carlo Caione <carlo@endlessm.com>
      Cc: huang lin <hl@rock-chips.com>
      Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
      Cc: Xu Ziyuan <xzy.xu@rock-chips.com>
      Cc: "jk.kernel@gmail.com" <jk.kernel@gmail.com>
      Cc: "Ariel D'Alessandro" <ariel@vanguardiasur.com.ar>
      Cc: Kever Yang <kever.yang@rock-chips.com>
      Cc: Samuel Egli <samuel.egli@siemens.com>
      Cc: Chin Liang See <clsee@altera.com>
      Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
      Cc: Hans de Goede <hdegoede@redhat.com>
      Cc: Ian Campbell <ijc@hellion.org.uk>
      Cc: Siarhei Siamashka <siarhei.siamashka@gmail.com>
      Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
      Cc: Andre Przywara <andre.przywara@arm.com>
      Cc: Bernhard Nortmann <bernhard.nortmann@web.de>
      Cc: Wolfgang Denk <wd@denx.de>
      Cc: Ben Whitten <ben.whitten@gmail.com>
      Cc: Tom Warren <twarren@nvidia.com>
      Cc: Alexander Graf <agraf@suse.de>
      Cc: Sekhar Nori <nsekhar@ti.com>
      Cc: Vitaly Andrianov <vitalya@ti.com>
      Cc: "Andrew F. Davis" <afd@ti.com>
      Cc: Murali Karicheri <m-karicheri2@ti.com>
      Cc: Carlos Hernandez <ceh@ti.com>
      Cc: Ladislav Michl <ladis@linux-mips.org>
      Cc: Ash Charles <ashcharles@gmail.com>
      Cc: Mugunthan V N <mugunthanvnm@ti.com>
      Cc: Daniel Allred <d-allred@ti.com>
      Cc: Gong Qianyu <Qianyu.Gong@freescale.com>
      Signed-off-by: NTom Rini <trini@konsulko.com>
      Acked-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
      Acked-by: NChin Liang See <clsee@altera.com>
      Tested-by: NStephen Warren <swarren@nvidia.com>
      Acked-by: NPaul Kocialkowski <contact@paulk.fr>
      067716ba
  19. 02 7月, 2016 1 次提交
  20. 06 5月, 2016 1 次提交
  21. 28 4月, 2016 1 次提交
    • T
      omap3: Reduce logic/overo SPL max image size · 2489a7e9
      Tom Rini 提交于
      While the OMAP3 has 64KiB of SRAM, per the TRM the download area is only
      from 0x40200000 to 0x4020F000 and exceeding that will cause failure to
      boot.  Further, we need to make sure that we don't run into
      SRAM_SCRATCH_SPACE_ADDR as once SPL is running we will write values
      there and would corrupt our running image.
      
      Cc: Adam Ford <aford173@gmail.com>
      Cc: Steve Sakoman <sakoman@gmail.com>
      Signed-off-by: NTom Rini <trini@konsulko.com>
      2489a7e9
  22. 26 4月, 2016 3 次提交
  23. 20 4月, 2016 4 次提交
  24. 26 3月, 2016 1 次提交
  25. 25 2月, 2016 1 次提交
  26. 16 2月, 2016 2 次提交
  27. 08 2月, 2016 4 次提交