Allow sending restart conditions upon direction change as this is
required by some chips.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Heiko Schocher <hs@denx.de>
Reviewed-by: NHeiko Schocher <hs@denxx.de>

These support the flat device tree. We want to use the dev_read_..()
prefix for functions that support both flat tree and live tree. So rename
the existing functions to avoid confusion.

In the end we will have:

   1. dev_read_addr...()    - works on devices, supports flat/live tree
   2. devfdt_get_addr...()  - current functions, flat tree only
   3. of_get_address() etc. - new functions, live tree only

All drivers will be written to use 1. That function will in turn call
either 2 or 3 depending on whether the flat or live tree is in use.

Note this involves changing some dead code - the imx_lpi2c.c file.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Make sure the driver writes the cmd_data register only once per
read transfer instead of doing so potentially repeatedly.

In case the read transfer didn't finish quickly enough, the loop
in the driver code would spin fast enough to write the same value
into the cmd_data register again before re-checking whether the
transfer completed, which would cause another spurious read transfer
on the bus.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>

Some platforms don't implement the enable status register at offset 0x9c.
The SPEAr600 platform is one of them. The recently added check to this
status register can't be performend on these platforms.

This patch introduces a new config option that can be enabled on such
platforms not supporting this register.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Reviewed-by: NHeiko Schocher <hs@denx.de>

This patch adds support for the PCI(e) based I2C cores. Which can be
found for example on the Intel Bay Trail SoC. It has 7 I2C controllers
implemented as PCI devices.

This patch also adds the fixed values for the timing registers for
BayTrail which are taken from the Linux designware I2C driver.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

This patch adds DM support to the designware I2C driver. It currently
supports DM and the legacy I2C support. The legacy support should be
removed, once all platforms using it have DM enabled.
Signed-off-by: NStefan Roese <sr@denx.de>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Heiko Schocher <hs@denx.de>

This patch prepares the designware I2C driver for the DM conversion.
This is mainly done by removing struct i2c_adapter from the functions
that shall be used by the DM driver version as well.
Signed-off-by: NStefan Roese <sr@denx.de>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Heiko Schocher <hs@denx.de>

Integrating set_speed() into dw_i2c_set_bus_speed() will make the
conversion to DM easier for this driver.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Heiko Schocher <hs@denx.de>

dw_i2c_enable() is used to dis-/en-able the I2C controller. It makes
sense to add such a function, as the controller is dis-/en-abled
multiple times in the code. Additionally, this function now checks,
if the controller is really dis-/en-abled. This code is copied
from the Linux I2C driver version.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

In preparation for the SoCFPGA support of the designware I2C driver,
convert this driver to the common CONFIG_SYS_I2C framework.

This patch converts all users of this driver, this is:

- ST spearxxx boards
- AXS101 (ARC700 platform)

I couldn't test this patch on those boards. Only compile tested for all
spear boards. And tested on SoCFPGA.
Signed-off-by: NStefan Roese <sr@denx.de>
Reviewed-by: NMarek Vasut <marex@denx.de>
Acked-by: NAlexey Brodkin <abrodkin@synopsys.com>
Tested-by: NAlexey Brodkin <abrodkin@synopsys.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Vipin Kumar <vk.vipin@gmail.com>
Cc: Jeroen Hofstee <jeroen@myspectrum.nl>

Include the i2c header and change the non confirming
functions to do so.

Cc: Heiko Schocher <hs@denx.de>
Signed-off-by: NJeroen Hofstee <jeroen@myspectrum.nl>
Acked-by: NHeiko Schocher <hs@denx.de>
[trini: Fix i2c_get_bus_num prototype]
Signed-off-by: NTom Rini <trini@ti.com>

As soon as all boards have their CONFIG_SYS_I2C_BASE defined in
configuration files instead of "asm/arch/hardware.h" it's safe to remove
the inclusion in question and make driver platform-independent.

Cc: Tom Rini <trini@ti.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Vipin Kumar <vipin.kumar@st.com>
Cc: Armando Visconti <armando.visconti@st.com>
Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>

Enhance the DesignWare I2C driver to support address length more
than 1 byte. This enhancement is required as some I2C slave
device such as EEPROM chip might have 16 bit address byte.
Signed-off-by: NChin Liang See <clsee@altera.com>
Acked-by: NAlexey Brodkin <Alexey.Brodkin@synopsys.com>
Cc: Tom Rini <trini@ti.com>
cc: Armando Visconti <armando.visconti@st.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Heiko Schocher <hs@denx.de>

Since we agreed on legacy implementation of "eeprom_{read|write}"
(http://patchwork.ozlabs.org/patch/295825/) I had to fix/make it work
again DesignWare I2C driver for cases when 1 EEPROM IC fake I2C with
anumber of "built-in" ICs with different chip addresses.
Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>

Cc: Tom Rini <trini@ti.com>
cc: Armando Visconti <armando.visconti@st.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Heiko Schocher <hs@denx.de>
Cc: Vipin KUMAR <vipin.kumar@st.com>
Cc: Tom Rix <Tom.Rix@windriver.com>
Cc: Mischa Jonker <mjonker@synopsys.com>
Cc: Kuo-Jung Su <dantesu@faraday-tech.com>

This delay applies to any data transfer on I2C bus.

For example 1kB data read with per-byte access (which happens if
environment is stored in I2C EEPROM) takes more than 10 seconds.

Moreover data bus driver has to care about bus state and data transfer,
but not about internal states of attached devices.
Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>

Cc: Tom Rini <trini@ti.com>
cc: Armando Visconti <armando.visconti@st.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Heiko Schocher <hs@denx.de>
Cc: Vipin KUMAR <vipin.kumar@st.com>
Cc: Tom Rix <Tom.Rix@windriver.com>
Cc: Mischa Jonker <mjonker@synopsys.com>

As it is stated in DesignWare I2C databook: writes to IC_TAR (0x4)
register succeed only when IC_ENABLE[0] is set to 0.
Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>

Cc: Tom Rini <trini@ti.com>
cc: Armando Visconti <armando.visconti@st.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Heiko Schocher <hs@denx.de>
Cc: Vipin KUMAR <vipin.kumar@st.com>
Cc: Tom Rix <Tom.Rix@windriver.com>
Cc: Mischa Jonker <mjonker@synopsys.com>

Signed-off-by: NWolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: NTom Rini <trini@ti.com>

There are three couple (hcnt/lcnt) of registers for each
speed (SS/FS/HS). The driver needs to set the proper couple
of regs according to what speed we are setting.
Signed-off-by: NArmando Visconti <armando.visconti@st.com>

In the newer versions of designware i2c IP there is the possibility
of configuring it with IC_EMPTYFIFO_HOLD_MASTER_EN=1, which basically
requires the s/w to generate the stop bit condition directly, as
the h/w will not automatically generate it when TX_FIFO is empty.

To avoid generation of an extra 0x0 byte sent as data, the
IC_STOP command must be sent along with the last IC_CMD.

This patch always writes bit[9] of ic_data_cmd even in the
older versions, assuming that it is a noop there.
Signed-off-by: NArmando Visconti <armando.visconti@st.com>

This patch adds the capability to switch between 10
different I2C busses (from 0 to 9).
Signed-off-by: NArmando Visconti <armando.visconti@st.com>

i2c_probe() is changed to reinit the i2c bus upon read failure.
This is naturally the case upon i2c bus probing.

Also, some printf messages upon read failure are removed. As they
would interfere with the "i2c probe" command.

Additionally, i2c_set_bus_speed() now returns 0, so that the
"i2c speed" command can be used.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Amit Virdi <amit.virdi@st.com>
Cc: Vipin Kumar <vipin.kumar@st.com>

The designware i2c controller must be turned off before
setting the speed in IC_CON register, as stated in the
section 6.3.1 of the dw_apb_i2c_db.pdf.
Signed-off-by: NMichel Sanches <michel.sanches@st.com>
Signed-off-by: NArmando Visconti <armando.visconti@st.com>
Signed-off-by: NAmit Virdi <amit.virdi@st.com>

Earlier, a driver exists in the u-boot source for designware i2c interface. That
driver was specific to spear platforms. This patch implements the i2c controller
as a generic driver which can be used by multiple platforms

The driver files are now renamed to designware_i2c.c and designware_i2c.h and
these are moved into drivers/i2c folder for reusability by other
platforms
Signed-off-by: NVipin Kumar <vipin.kumar@st.com>
Signed-off-by: NAmit Virdi <amit.virdi@st.com>

I executed 'find . -name "*.[chS]" -perm 755 -exec chmod 644 {} \;'
Signed-off-by: NThomas Weber <swirl@gmx.li>
Add some more: neither Makefile nor config.mk need execute permissions.
Signed-off-by: NWolfgang Denk <wd@denx.de>

SPEAr SoCs contain a synopsys i2c controller.
This patch adds the driver for this IP.
Signed-off-by: NVipin <vipin.kumar@st.com>

SPEAr SoCs contain a synopsys i2c controller.
This patch adds the driver for this IP.
Signed-off-by: NVipin <vipin.kumar@st.com>