Remove 115200 from "earlycon" to avoid loss of initial
log messages during linux kernel 4.1  bootup
Signed-off-by: NPratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

This patch also expose the complete DDR region(s) to Linux.
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: NMingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

DDR errata-A008378 applies to LS1021-20-22A-R1.0, T1023-R1.0,
T1024-R1.0, T1040-42-20-22-R1.0/R1.1, it has been fixed on
LS102x Rev2.
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

move arch/powerpc/include/asm/fsl_errata.h to include/fsl_errata.h
to make it public for both ARM and POWER SoCs.
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
[York Sun: fix soc.h path in fsl_errata.h]
Reviewed-by: NYork Sun <yorksun@freescale.com>

Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

When creating phy-handle property, an unsigned int value is created by
fdt_create_phandle, and memcpy is used to get the value, since DTS is
big endian, the value cannot be used directly on little endian SoCs,
it should be converted by cpu_to_fdt32.
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

When 4 chip-selects are used, vref should use range 1 and CDT uses 80 ohm,
and 2T timing is enabled.
Signed-off-by: NYork Sun <yorksun@freescale.com>

When 4 chip-selects are used, vref should use range 1 and CDT uses 80 ohm,
and 2T timing is enabled.
Signed-off-by: NYork Sun <yorksun@freescale.com>

In case four chip-selects are all active, the turnaround times need to
increase to avoid overlapping under heavy load.
Signed-off-by: NYork Sun <yorksun@freescale.com>

The workaround requires different setting for range 1 vs 2.
Also adjust timeout value for waiting for controller to be idle.
Signed-off-by: NYork Sun <yorksun@freescale.com>

For four chip-selects enabled case, RTT is parked on all of them.
Signed-off-by: NYork Sun <yorksun@freescale.com>

MR6 bit 6 is set accrodingly for range 1 or 2, per JEDEC spec.
Signed-off-by: NYork Sun <yorksun@freescale.com>

DDR4 has different RTT value and code according to JEDEC spec. Update
the macros and options .
Signed-off-by: NYork Sun <yorksun@freescale.com>

Add xlnx,xps-spi-2.00.a/b which is compatible string
listed in the Linux kernel.
Remove origin one which has no real background.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NJagan Teki <jteki@openedev.com>

Used quite different name's and e-mail address, all of
them mapped to standard name and e-mail address.

Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NJagan Teki <jteki@openedev.com>

Since all spi-flash core operations are moved into
sf_ops.c then it's better to renamed as spi-flash.c
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NJagan Teki <jteki@openedev.com>

Used static for file-scope functions in sf_probe.c
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NJagan Teki <jteki@openedev.com>

Since spi_slave is a spi pointer in spi_flash{} then assign
spi_slave{} pointer to flash->spi and remove spi_slave
pointer argument to
- spi_flash_probe_slave
- spi_flash_scan
Tested-by: NJagan Teki <jteki@openedev.com>
Tested-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NJagan Teki <jteki@openedev.com>

For assigning read_bar commands in spansion case, break
is missing this patch add that break.
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NJagan Teki <jteki@openedev.com>

SST parts added on sf_params.c supports both SST_WR which consits
of both BP and WP and there is a spi controller ich which supports
only BP so the relevent _write hook set based on "slave->op_mode_tx"
hence there is no respective change required from flash side hance
removed these.
Tested-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Signed-off-by: NJagan Teki <jteki@openedev.com>

Removed unneeded header includes in sf_ops and sf_probe
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NJagan Teki <jteki@openedev.com>

Using macro's for flash power up read-only access code
leads wrong behaviour hence use idcode0 for runtime
detection, hence the flash which require this functionality
gets detected at runtime.
Tested-by: NJagan Teki <jteki@openedev.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NJagan Teki <jteki@openedev.com>

Most of the register access function are static,
so used simple name to represent each.
Tested-by: NJagan Teki <jteki@openedev.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NJagan Teki <jteki@openedev.com>

This patch removes unneeded ifdef and fixed accordingly.
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NJagan Teki <jteki@openedev.com>

Use static for file-scope functions and removed
them from header files.
Tested-by: NJagan Teki <jteki@openedev.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Signed-off-by: NJagan Teki <jteki@openedev.com>

- Move bar read code below the bar write hance both
  at once place, hence it easy for #ifdef macro only
  once and readable.
- Move read_cmd_array at top
Tested-by: NJagan Teki <jteki@openedev.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NJagan Teki <jteki@openedev.com>

read_id code is related to spi_flash stuff
hence moved to sf_ops.
Tested-by: NJagan Teki <jteki@openedev.com>
Tested-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NJagan Teki <jteki@openedev.com>

Intension is that sf_ops should deals all spi_flash
related stuff and sf_probe (which should renamed future)
should be an interface layer for spi_flash versus spi drivers.

sf_ops => spi_flash interface
sf_probe => interface layer vs spi_flash(sf_probe) to spi drivers
Tested-by: NJagan Teki <jteki@openedev.com>
Tested-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NJagan Teki <jteki@openedev.com>

Rename spi_flash_validate_params to spi_flash_scan
as this code not only deals with params setup but
also configure all spi_flash attributes.

And also moved all flash related code into
spi_flash_scan for future functionality addition.
Tested-by: NJagan Teki <jteki@openedev.com>
Tested-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NJagan Teki <jteki@openedev.com>

ZynqMP is using different symbol.
Use correct one.
Reviewed-by: NJagan Teki <jteki@openedev.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Extend compatible list table for cdns,spi-r1p6 compatible string.
Reviewed-by: NJagan Teki <jteki@openedev.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Support qspi flashes for mx7dsabresd
1. introduce pin mux settings
2. enable qspi clock
3. introduce related macro definitions

Default QSPI is not enabled, since we need hardware rework to use QSPI,
see SPF-28590, page 9:
"
QSPI signals are muxed with EPDC_D[7:0]
When using QSPI: de-populate R388-R391, R396-R399
populate R392-R395, R299, R300
"

After hardware rework, define CONFIG_FSL_QSPI in mx7dsabresd.h. qspi
flashes can be deteced and read/erase/write. Log info:
"
=> sf probe
SF: Detected MX25L51235F with page size 256 Bytes, erase size 64 KiB, total 64 MiB
=> sf read 0x80000000 0 0x4000000
device 0 whole chip
SF: 67108864 bytes @ 0x0 Read: OK
=> sf erase 0 0x4000000
SF: 67108864 bytes @ 0x0 Erased: OK
=> sf write 0x80000000 0 0x4000000
device 0 whole chip
SF: 67108864 bytes @ 0x0 Written: OK
"

Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Adrian Alonso <aalonso@freescale.com>
Reviewed-by: NStefano Babic <sbabic@denx.de>
Reviewed-by: NJagan Teki <jteki@openedev.com>
Signed-off-by: NPeng Fan <Peng.Fan@freescale.com>

SPI_3WIRE is spi mode not spi flags, so this patch fixed
the spi-3wire checking throgh mode instead of flags.

Cc: Mugunthan V N <mugunthanvnm@ti.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NJagan Teki <jteki@openedev.com>

spi-3wire is used when SI/SO signals shared so get
the same from dts node and assign to mode on slave
plat->mode.
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NJagan Teki <jteki@openedev.com>

Use tabs instead of space for indentation.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Fix typo in command description.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Fix incorrect comment alignments.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>