Sync from Linux commit a188339ca5a3 ("Linux 5.2-rc1")
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>

This board still doesn't select CONFIG_DM and seems to be umaintained.
As it makes progress on modernizing several DaVinci drivers more
difficult and the maintainer has not expressed interest in updating
it, this patch proposes to remove it.
Signed-off-by: NBartosz Golaszewski <bgolaszewski@baylibre.com>

This board still doesn't select CONFIG_DM and seems to be umaintained.
As it makes progress on modernizing several DaVinci drivers more
difficult and the maintainer has not expressed interest in updating
it, this patch proposes to remove it.
Signed-off-by: NBartosz Golaszewski <bgolaszewski@baylibre.com>
Acked-by: NStefano Babic <sbabic@denx.de>

This board still doesn't select CONFIG_DM and seems to be umaintained.
As it makes progress on modernizing several DaVinci drivers more
difficult and the maintainer has not expressed interest in updating
it, this patch proposes to remove it.
Signed-off-by: NBartosz Golaszewski <bgolaszewski@baylibre.com>
Acked-by: NStefano Babic <sbabic@denx.de>

This board still doesn't select CONFIG_DM and seems to be umaintained.
As it makes progress on modernizing several DaVinci drivers more
difficult and the maintainer has not expressed interest in updating
it, this patch proposes to remove it.
Signed-off-by: NBartosz Golaszewski <bgolaszewski@baylibre.com>

This board still doesn't select CONFIG_DM and seems to be umaintained.
As it makes progress on modernizing several DaVinci drivers more
difficult and the maintainer has not expressed interest in updating
it, this patch proposes to remove it.
Signed-off-by: NBartosz Golaszewski <bgolaszewski@baylibre.com>
Acked-by: NHeiko Schocher <hs@denx.de>

This board still doesn't select CONFIG_DM and seems to be umaintained.
As it makes progress on modernizing several DaVinci drivers more
difficult and the maintainer has not expressed interest in updating
it, this patch proposes to remove it.
Signed-off-by: NBartosz Golaszewski <bgolaszewski@baylibre.com>

This board still doesn't select CONFIG_DM and seems to be umaintained.
As it makes progress on modernizing several DaVinci drivers more
difficult and the maintainer has not expressed interest in updating
it, this patch proposes to remove it.
Signed-off-by: NBartosz Golaszewski <bgolaszewski@baylibre.com>
Acked-by: NStefano Babic <sbabic@denx.de>

This board still doesn't select CONFIG_DM and seems to be umaintained.
As it makes progress on modernizing several DaVinci drivers more
difficult and the maintainer has not expressed interest in updating
it, this patch proposes to remove it.
Signed-off-by: NBartosz Golaszewski <bgolaszewski@baylibre.com>

Add a driver which supports transmitting digital sound to an audio codec.
This uses fixed parameters as a device-tree binding is not currently
defined.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Acked-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Add a driver for the audio hub. This is modelled as a misc device which
supports writing audio data from I2S.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Acked-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

This function enables a peripheral clock and then immediately sets its
divider. Add a delay to allow the clock to settle first. This matches the
delay in other places which do a similar thing.

Without this, the I2S device on Nyan does not init properly.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NTom Warren <twarren@nvidia.com>

The first clock type appears to have and incorrect setting for out of the
mux outputs. It should be CLK_M, not OSC. Fix it and its only user.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Finding bitstream from cff-file is no longer valid after bitstream is built
into FIT image and loaded by generic firmware loader. Remove cff-file
as this is legacy implementation from A10 downstream.
Signed-off-by: NTien Fong Chee <tien.fong.chee@intel.com>

On SoCFPGA A10 systems, it can rarely happen that a reboot from Linux
will result in stale data in PL310 L2 cache controller. Even if the L2
cache controller is disabled via the CTRL register CTRL_EN bit, those
data can interfere with operation of devices using DMA, like e.g. the
DWMMC controller. This can in turn cause e.g. SPL to fail reading data
from SD/MMC.

The obvious solution here would be to fully reset the L2 cache controller
via the reset manager MPUMODRST L2 bit, however this causes bus hang even
if executed entirely from L1 I-cache to avoid generating any bus traffic
through the L2 cache controller.

This patch thus configures and enables the L2 cache controller very early
in the SPL boot process, clears the L2 cache and disables the L2 cache
controller again.

The reason for doing it in SPL is because we need to avoid accessing any
of the potentially stale data in the L2 cache, and we are certain any of
the stale data will be below the OCRAM address range. To further reduce
bus traffic during the L2 cache invalidation, we enable L1 I-cache and
run the invalidation code entirely out of the L1 I-cache.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>

Pull the PL310 clearing code into common code, so it can be reused
by Arria10.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>

Manage power supply configuration for board using stpmic1
with LPDDR2 or with LPDDR3:
+ VDD_DDR1 = 1.8V with BUCK3 (bypass if possible)
+ VDD_DDR2 = 1.2V with BUCK2
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>

Update DDR configuration with the latest update:

- PUBL_regs: DXnGCR[0]= according to ddr_width to disable Byte
                        lane 2/3 in 16bit
- fix LPDDR2/3 timing_calc to step RL/WL in relaxed
  timings mode
- remove  LPDDR3 RL3 (optional) support vs  MR0[7]
  because MR0[7] can't be read instead  always apply
  worse RL/WL for LPDDR3 when freq < 166MHz)
- change  MR3 to 48ohm drive  for LPDDR2/3
- change default ZPROG[7:4] = 0x1 for LPDDR2/3 ,
  '0' is not allowed even when ODT not used
- use DQSTRN for LPDDR2/3 (it was not set in PIR)
- LPDDR3: set dqsge/dwsgx gate extension to 2,2
  like LPDDR2
-DDRCTRL.dfitmg0:
  + for LPDDR3 tphy_wrlat = WL (as LPDDR2)
  + improvement for relaxed mode vs  RL/Wl at corner case.
    For example @533MHz RL/WL (relaxed) = 9/5 for LPDDR2/3
    and correction to MR2 accordingly
- DDR_PCFGQOS1_1: port1 timeout relaxed from 0x00 to 0x40,
  for LTDC.
- DDR_PCFGWQOS0_0: change vpr level from
  11 to 12 in order to include the CPU on
  the variable priority queue.
- DDR_SCHED: fix to consider 13 levels  (13 levels - 1 = 0xC)
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>

Allow fractional support in DDR tools.
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>

Add the needed configurations for bootstage and
activate bootstage command.

BOOTSTAGE_REPORT is not activated by default.
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>

In initf_bootstage() we call bootstage_mark_name() which ends up calling
timer_get_us() before timer_init(); that cause crash for stm32mp1.

This patch solve the issue without changing the initialization sequence.
See also commit 97d20f69 ("Enable CONFIG_TIMER_EARLY with bootstage")
for other solution when DM is activated for TIMER.
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>

Activate bootcount and use TAMP register to store the count value.
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>

Use SGI0 interruption  and TAMP_BACKUP_MAGIC_NUMBER
to synchronize the core1 boot sequence requested by
core0 in psci_cpu_on():
- a initial interruption is needed in ROM code after
  RCC_MP_GRSTCSETR_MPUP1RST (psci_cpu_off)
- the ROM code set to 0 the 2 registers
  + TAMP_BACKUP_BRANCH_ADDRESS
  + TAMP_BACKUP_MAGIC_NUMBER
  when magic is not egual to
  BOOT_API_A7_CORE0_MAGIC_NUMBER

This patch solve issue for cpu1 restart in kernel.
echo 0 > /sys/devices/system/cpu/cpu1/online
echo 1 > /sys/devices/system/cpu/cpu1/online
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>

Reorder the include files in alphabetic order.
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>

Use Kconfig to activate CONFIG_PREBOOT (empty by default).
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>

Add arch stm32mp for ENV migration step and drop more
items from include/configs/xxx.h.
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>

This patch moves the the config SYS_MALLOC_LEN to
Kconfig as it is already done for zynq arch in
commit 01aa5b8f ("Kconfig: Move config
SYS_MALLOC_LEN to Kconfig for zynq")
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>

Signed-off-by: NZhao Qiang <qiang.zhao@nxp.com>
Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on
CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE
is enabled
Signed-off-by: NUdit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

Move the ecc addr from driver to dts.
Signed-off-by: NPeng Ma <peng.ma@nxp.com>
Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

LS1028AQDS Development System is a high-performance
computing, evaluation, and development platform that supports
LS1028A QorIQ Architecture processor.
Signed-off-by: NSudhanshu Gupta <sudhanshu.gupta@nxp.com>
Signed-off-by: NRai Harninder <harninder.rai@nxp.com>
Signed-off-by: NRajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: NBhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Signed-off-by: NTang yuantian <andy.tang@nxp.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

LS1028A is an ARMv8 implementation. LS1028ARDB is an evaluation
platform that supports the LS1028A family SoCs. This patch add basic
support of the platform.
Signed-off-by: NSudhanshu Gupta <sudhanshu.gupta@nxp.com>
Signed-off-by: NRai Harninder <harninder.rai@nxp.com>
Signed-off-by: NRajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: NBhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Signed-off-by: NTang Yuantian <andy.tang@nxp.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

Ls1028a SoC is based on Layerscape Chassis Generation 3.2
architecture with features:
 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN
 ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers,
 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc.
Signed-off-by: NSudhanshu Gupta <sudhanshu.gupta@nxp.com>
Signed-off-by: NRai Harninder <harninder.rai@nxp.com>
Signed-off-by: NRajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: NBhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Signed-off-by: NTang Yuantian <andy.tang@nxp.com>
Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

The LX2160A integrated 6 PCIe Gen4 controllers.
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

The LX2160A PCIe is using driver PCIE_LAYERSCAPE_GEN4 instead
of PCIE_LAYERSCAPE.
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

The lx2160a have up to 6 PCIe controllers and have different
address and size of PCIe region.
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

The LS2080A has 8GB region for each PCIe controller, while the
other platforms have 32GB.
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

Change to use PCIe address macro to determine if precompile the PCIe
MMU table entry.
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

Build an SPL which can be started via SCIF download mode on R-Car Gen3
and allows loading and executing U-Boot uImage with the next stage code.
This is also useful for starting e.g. ATF BL2, which inits the hardware
and returns to the U-Boot SPL, which can then load e.g. U-Boot proper.

The H3, M3-W, M3-N SoCs have plenty of SRAM for storing the U-Boot SPL
while the payload, e.g. ATF BL2, executes, so there is no problem here.

However, E3 and D3 have much less SRAM, hence the loader uses a trick
where it copies itself beyond the area used by BL2 and executes from
there. That area is 32kiB large and not enough to hold U-Boot SPL, BSS,
stack and malloc area, so the later two are placed at +0x4000 offset
from start of SRAM, another area not used by ATF BL2. To make things
even more complicated, the SCIF loader cannot load to the upper 32kiB
of the SRAM directly, hence the copying approach.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Some H6 boards have a watchdog which didn't make the SoC
reboot properly.

Reason is still unknown but several people have test it.
Chen-Yu Tsai :
Pine H64 = H6 V200-AWIN H6448BA 7782 => OK
OrangePi Lite 2 = H6 V200-AWIN H8068BA 61C2 => KO

Martin Ayotte :
Pine H64 = H8069BA 6892 => OK
OrangePi 3 = HA047BA 69W2 => KO
OrangePi One Plus = H7310BA 6842 => KO
OrangePi Lite2 = H6448BA 6662 => KO

Clément Péron:
Beelink GS1 = H6 V200-AWIN H7309BA 6842 => KO

After the series of result, Icenowy try to reach Allwinner about this
issue but they seems not interested to investigate it.

As we don't have the ARIS coproc to do power management and watchdogis
the only solution to reset the board.

So, Change from watchdog to R_watchdog to allow a reboot on all H6
boards.
Signed-off-by: NClément Péron <peron.clem@gmail.com>
Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>