- 11 2月, 2017 1 次提交
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- 10 2月, 2017 11 次提交
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由 Eddie Cai 提交于
Miniarm is the internal project code. Now it is officially named Tinker board. So rename it. Signed-off-by: NEddie Cai <eddie.cai@rock-chips.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Romain Perier 提交于
This commit enables ethernet MAC address randomization on the firefly-rk3288. It removes the error at startup 'ethernet@ff290000 address not set'. Signed-off-by: NRomain Perier <romain.perier@collabora.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Jacob Chen 提交于
Keep it same with other boards otherwise i have to write special script for it.. Signed-off-by: NJacob Chen <jacob2.chen@rock-chips.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Jacob Chen 提交于
To reduce redundant code. Signed-off-by: NJacob Chen <jacob2.chen@rock-chips.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
This is wrong at present, so genboardscfg.py gives the following warnings: WARNING: no status info for 'chromebook_minnie' WARNING: no maintainers for 'chromebook_minnie' Fix it. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Jacob Chen 提交于
miniarm board use lpddr3 Signed-off-by: NJacob Chen <jacob2.chen@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org> Added 'rockchip:' prefix to subject: Signed-off-by: NSimon Glass <sjg@chromium.org> Change-Id: I84c3679dab2dbd8d01c1ebfd22220946d07c03cd
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由 Tom Rini 提交于
It was incorrect to always include "asm/arch-omap3/mux.h" constantly. This introduced warnings on non-omap3 where certain values will conflict between the various families. Conditionally guard the inclusion in order to correct the problem. Fixes: 6aca17c9 ("drivers: mmc: omap_hsmmc: Fix IO Buffer on OMAP36xx") Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Tom Rini 提交于
To save more space, switch to simple malloc here. Signed-off-by: NTom Rini <trini@konsulko.com>
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- 09 2月, 2017 28 次提交
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由 Tom Rini 提交于
The qemu-x86* targets do not want to enable this. Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Fiach Antaw 提交于
MMC devices accessed exclusively via the driver model were not being initialized before being exposed as block devices, causing issues in scenarios where the MMC device is first accessed via the uclass block interface. Signed-off-by: NFiach Antaw <fiach.antaw@uqconnect.edu.au>
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由 Adam Ford 提交于
On the OMAP36xx/37xx the CONTROL_WKUP_CTRL register has a field (bit 6) named GPIO_IO_PWRDNZ. If 0, the IO buffers which are related to GPIO_126, 127 and 129 are disabled. Some boards may need this for MMC. After the PBIAS is configured, this bit should be set high to enable these GPIO pins. Signed-off-by: NAdam Ford <aford173@gmail.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Jaehoon Chung 提交于
ftsdc021_sdhci.c is dead file. There is no reason to maintain this host controller. Removes the entire ftsdc021_sdhci.c. Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Jaehoon Chung 提交于
If there are alias nodes as "mmc", use the devnum as alias index number. This patch is for fixing a problem of Exynos4 series. Problem is the below thing. Current legacy mode: EXYNOS DWMMC: 0, SAMSUNG SDHCI: 1 After using DM: SAMSUNG SDHCI: 0, EXYNOS DWMMC: 1 Dev index is swapped. Then u-boot can't find the kernel image..because it is already set to 0 as mmcdev. If change from legacy to DM, also needs to touch all exynos4 config file. For using simply, just supporting the fixed devnum with alias node is better than it. Usage: alaise { .... mmc0 = &sdhci2; /* eMMC */ mmc1 = &sdhci1; /* SD */ ... } Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Jaehoon Chung 提交于
To use driver-model adds the pmic node for max8997. This is used as kernel device-tree in Linux. Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Jaehoon Chung 提交于
Add the max8997 controller for Driver model. Exynos4210 is using max8997 pmic controller. (pmic_max8997.c should be deprecated.) Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 John Haechten 提交于
Signed-off-by: NJohn Haechten <john.haechten@microsemi.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Robert P. J. Day 提交于
Signed-off-by: NRobert P. J. Day <rpjday@crashcourse.ca>
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由 Lars Poeschel 提交于
Albeit it's a typo, neither CONGIG_CMD_STORAGE nor CONFIG_CMD_STORAGE are used anywhere, so remove the define from the board configs. Signed-off-by: NLars Poeschel <poeschel@lemonage.de> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Masahiro Yamada 提交于
CONFIG_CMD_ZIP is not defined by any board. I am moving CONFIG_CMD_UNZIP to defconfig files except UniPhier SoC family. I am the maintainer of UniPhier platform, so I know "select CMD_UNZIP" is better for this platform. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Acked-by: NMichal Simek <michal.simek@xilinx.com> Acked-by: NStefan Roese <sr@denx.de> Acked-by: NRyan Harkin <ryan.harkin@linaro.org> Tested-by: NRyan Harkin <ryan.harkin@linaro.org>
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由 Masahiro Yamada 提交于
There are two typos in the comment "invalide i-cache is enabled". We can fix it by invalide -> invalidate is -> if Or, if we want to match the comment to the code, we can say "skip invalidating i-cache if disabled". Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Phil Edworthy 提交于
CONFIG_SPL_STACK_SIZE is not a config option, so rename it. Signed-off-by: NPhil Edworthy <phil.edworthy@renesas.com>
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由 Keerthy 提交于
The array indices used currently are dispalaced by 1 for SMPS6 through SMPS10 in the respective places of voltage and ctrl arrays hence fix the same as to assign the right voltage and ctrl registers. Signed-off-by: NKeerthy <j-keerthy@ti.com>
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由 Masahiro Yamada 提交于
Both CONFIG_PWM_TEGRA and CONFIG_PWM_EXYNOS depend on CONFIG_DM_PWM, i.e. they are already guarded by Kconfig correctly. Remove unneeded ifdef CONFIG_DM_PWM ... endif. While we are here, let's tidy up alignment and sort the lines alphabetically in Makefile. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Jean-Jacques Hiblot 提交于
The default values for the configuration defines CONFIG_ENV_SPI_xxx are arbitrary values. It makes more sense to set them to the values used by the sf command. Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Albert ARIBAUD \(3ADEV\) 提交于
The sequence erroneously launched the DDR controller initialization before the pad muxing was done, causing DRAM size computation to hang. Configuring the pads first then launching DDR controller initialization prevents the DRAM hanging. Signed-off-by: NAlbert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
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由 Lokesh Vutla 提交于
cpsw driver tries to get macid for am43xx SoCs using the compatible ti,am4372. But not all variants of am43x uses this complatible like epos evm uses ti,am438x. So use a generic compatible ti,am43 to get macid for all am43 based platforms. Tested-by: NAparna Balasubramanian <aparnab@ti.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Reviewed-by: NJoe Hershberger <joe.hershberger@ni.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Grygorii Strashko 提交于
Now when CONFIG_CMD_IMLS_NAND is enabled the u-boot build will fail, because nand_read_skip_bad() function has been changed to accept more parameters, hence fix it. CC cmd/bootm.o cmd/bootm.c: In function 'nand_imls_legacyimage': cmd/bootm.c:390:8: error: too few arguments to function 'nand_read_skip_bad' ret = nand_read_skip_bad(mtd, off, &len, imgdata); ^ In file included from cmd/bootm.c:18:0: include/nand.h:101:5: note: declared here int nand_read_skip_bad(struct mtd_info *mtd, loff_t offset, size_t *length, ^ LD drivers/block/built-in.o Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Dan Murphy 提交于
Pick commit 66b47b4a9dad0 checkpatch: look for common misspellings from the Linux kernel for spelling check from Kees Cook In addition pulled in additional changes commit ebfd7d6237531 checkpatch: add optional --codespell dictionary to find more typos from the Linux kernel for codespell from Joe Perches commit f1a63678554f8 checkpatch: remove local from codespell path from the Linux kernel for dictionary path from Maxim Uvarov Signed-off-by: NDan Murphy <dmurphy@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Emmanuel Vadot 提交于
Now that we have a Kconfig for the API, convert the two boards that are using this to Kconfig and remove CONFIG_API from the whitelist. Signed-off-by: NEmmanuel Vadot <manu@bidouilliste.com> Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Emmanuel Vadot 提交于
Add kconfig file to enable API support Signed-off-by: NEmmanuel Vadot <manu@bidouilliste.com> Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Masahiro Yamada 提交于
Use the kbuild style log. Prior to this commit: ./scripts/check-config.sh u-boot.cfg \ ./scripts/config_whitelist.txt . 1>&2 With this commit: CFGCHK u-boot.cfg Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Lokesh Vutla 提交于
As reported in [1], rename the k2* dts files to keystone-* files this will force consistency throughout. Script for the same (and hand modified for Makefile and config files): for i in arch/arm/dts/k2* do b=`basename $i`; git mv $i arch/arm/dts/keystone-$b; sed -i -e "s/$b/keystone-$b/g" arch/arm/dts/*[si] done This is similar to linux kernel commit 5edafc29829bc ("ARM: dts: k2*: Rename the k2* files to keystone-k2* files") [1] http://marc.info/?l=linux-arm-kernel&m=145637407804754&w=2Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 maxims@google.com 提交于
Fix H-PLL and M-PLL rate calculation in ast2500 clock driver. Without this fix, valid setting can lead to division by zero when requesting the rate of H-PLL or M-PLL clocks. Signed-off-by: NMaxim Sloyko <maxims@google.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Vincent Tinelli 提交于
On some cases the first 440 bytes of MBR are used to keep an additional information for ROM boot loader. 'gpt write' command doesn't preserve that area and makes boot code gone. Preserve boot code area when run 'gpt write' command. Signed-off-by: NVincent Tinelli <vincent.tinelli@intel.com> Signed-off-by: NBrennan Ashton <brn@deako.com> Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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