- 16 5月, 2020 1 次提交
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由 Trevor Woerner 提交于
Have this symbol follow the pattern of all other such symbols. This patch removes a TODO from the code. Signed-off-by: NTrevor Woerner <twoerner@gmail.com>
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- 10 5月, 2020 1 次提交
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由 Ye Li 提交于
For dual ethernet controllers, the HW design may connect ETH phys to one MDIO ports. So two different ethernet drivers have to share MDIO bus. Since two ethernet drivers are independent, we can't ensure their probe order. To resolve this problem, introduce an eth phy generic driver and uclass. After eth-uclass binds, we search the mdio node and binds the phy node with the eth-phy-generic driver. When one eth driver get its phy device, the parent of phy device will probe prior than phy device. So this ensure the eth driver ownes the MDIO bus will be probed before using its MDIO. Signed-off-by: NYe Li <ye.li@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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- 01 5月, 2020 1 次提交
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由 Marek Vasut 提交于
Add support for U-Boot DM and DT probing. Furthermore, build the SMC911x standalone EEPROM example only for the non-DM case, as it is not converted yet. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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- 29 4月, 2020 1 次提交
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由 Ioana Ciornei 提交于
Add a driver for the MDIO interface integrated in the mEMAC (Multi-rate Ethernet Media Access Controller) and the Fman 10G Ethernet MACs. Signed-off-by: NIoana Ciornei <ioana.ciornei@nxp.com> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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- 30 1月, 2020 1 次提交
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由 Amit Singh Tomar 提交于
The Broadcom GENET Ethernet MACs are used in several MIPS based SoCs and in the Broadcom 2711/2838 SoC used on the Raspberry Pi 4. There is no publicly available documentation, so this driver is based on the Linux driver. Compared to that the queue management is drastically simplified, also we only support version 5 of the IP and RGMII connections between MAC and PHY, as used on the RPi4. Signed-off-by: NAmit Singh Tomar <amittomer25@gmail.com> Reviewed-by: NAndre Przywara <andre.przywara@arm.com> [Andre: heavy cleanup and a few fixes] Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Tested-by: NCorentin Labbe <clabbe@baylibre.com> Signed-off-by: NMatthias Brugger <mbrugger@suse.com>
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- 10 1月, 2020 1 次提交
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由 Angelo Durgehello 提交于
Add ColdFire fec to Kconfig. Signed-off-by: NAngelo Durgehello <angelo.dureghello@timesys.com>
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- 09 12月, 2019 1 次提交
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由 Nevo Hed 提交于
Changes to mvpp2.c require the MVMDIO module which in turn uses DM_MDIO. Signed-off-by: NNevo Hed <nhed+github@starry.com> Reviewed-by: NRamon Fried <rfried.dev@gmail.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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- 05 11月, 2019 1 次提交
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由 Peng Fan 提交于
Make FEC driver could be used by i.MX8M when CONFIG_FEC_MXC defined in defconfig. Signed-off-by: NPeng Fan <peng.fan@nxp.com> Reviewed-by: NFrieder Schrempf <frieder.schrempf@kontron.de> Tested-by: NFrieder Schrempf <frieder.schrempf@kontron.de>
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- 25 10月, 2019 1 次提交
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由 Weijie Gao 提交于
The mt7628 has an embedded ethernet switch (5 phy ports + 1 cpu port). Although in IOT mode only port0 is usable, the phy0 is still connected to the switch, not the ethernet gmac directly. This patch rewrites it and makes it optional. It can be turned on by adding mediatek,poll-link-phy = <?> explicitly into the eth node. By default the driver is switch mode with all 5 phy ports working without link detection. Signed-off-by: NWeijie Gao <weijie.gao@mediatek.com>
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- 05 9月, 2019 4 次提交
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由 Alex Marginean 提交于
This patch adds a separate driver for the MDIO interface of the Marvell Ethernet controllers based on driver model. There are two reasons to have a separate driver rather than including it inside the MAC driver itself: *) The MDIO interface is shared by all Ethernet ports, so a driver must guarantee non-concurrent accesses to this MDIO interface. The most logical way is to have a separate driver that handles this single MDIO interface, used by all Ethernet ports. *) The MDIO interface is the same between the existing mv643xx_eth driver and the new mvneta/mvpp2 driver. Even though it is for now only used by the mvneta/mvpp2 driver, it will in the future be used by the mv643xx_eth driver as well. This driver supports SMI IEEE for 802.3 Clause 22 and XSMI for IEEE 802.3 Clause 45. This patch also adds device tree binding for marvell MDIO driver. Signed-off-by: NKen Ma <make@marvell.com> Signed-off-by: NAlex Marginean <alexm.osslist@gmail.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Florinel Iordache 提交于
Create drivers/net/fsl-mc/Kconfig and move fsl-mc specific configs from arch/arm/cpu/armv8/fsl-layerscape/Kconfig to this new Kconfig Signed-off-by: NFlorinel Iordache <florinel.iordache@nxp.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Alex Marginean 提交于
This driver is used for MDIO muxes driven over I2C. This is currently used on Freescale LS1028A QDS board, on which the physical MDIO MUX is controlled by an on-board FPGA which in turn is configured through I2C. Signed-off-by: NAlex Marginean <alexm.osslist@gmail.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Joe Hershberger 提交于
This reverts commit d9a9174f.
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- 29 7月, 2019 1 次提交
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由 Keerthy 提交于
commit 49116e6d ("doc: arch: Convert README.sandbox to reST") Moves README.sandbox to doc/arch. Replace all the existing instances to point to the right documentation file. Signed-off-by: NKeerthy <j-keerthy@ti.com>
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- 26 7月, 2019 3 次提交
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由 Alex Marginean 提交于
This driver is used for MDIO muxes driven over I2C. This is currently used on Freescale LS1028A QDS board, on which the physical MDIO MUX is controlled by an on-board FPGA which in turn is configured through I2C. Signed-off-by: NAlex Marginean <alexm.osslist@gmail.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Alex Marginean 提交于
Adds a driver for the MDIO interface currently integrated in LS1028A SoC. This MDIO interface is shared by multiple ethernet interfaces and is presented as a stand-alone PCI function on the SoC ECAM. Ethernet has a functional dependency on MDIO, for simplicity there is a single config option for both. Signed-off-by: NAlex Marginean <alexm.osslist@gmail.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Alex Marginean 提交于
Adds a driver for NXP ENETC ethernet controller currently integrated in LS1028A. ENETC is a fairly straight-forward BD ring device and interfaces are presented as PCI EPs on the SoC ECAM. Signed-off-by: NCatalin Horghidan <catalin.horghidan@nxp.com> Signed-off-by: NAlex Marginean <alexm.osslist@gmail.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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- 19 7月, 2019 3 次提交
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由 Lukasz Majewski 提交于
The fec_mxc.c driver can be reused by i.MX28 when DM_ETH is enabled. One only needs to add proper compatible and dependency on FEC_MXC in the Kconfig. Signed-off-by: NLukasz Majewski <lukma@denx.de> Reviewed-by: NMarek Vasut <marex@denx.de>
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由 Alex Marginean 提交于
Adds a test using a makeshift MDIO MUX. The test is based on the existing MDIO test. It uses the last emulated PHY register to verify MUX selection. Signed-off-by: NAlex Marginean <alexm.osslist@gmail.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Alex Marginean 提交于
Adds a class for MDIO MUXes, which control access to a series of downstream child MDIOs. MDIO MUX drivers are required to implement a select function used to switch between child buses. MUX children are registered as MDIO buses and they can be used just like regular MDIOs. Signed-off-by: NAlex Marginean <alexm.osslist@gmail.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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- 16 7月, 2019 2 次提交
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由 Alex Marginean 提交于
A very simple test for DM_MDIO, mimicks a register write/read through the sandbox bus to a dummy PHY. Signed-off-by: NAlex Marginean <alexm.osslist@gmail.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Tested-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Alex Marginean 提交于
Adds UCLASS_MDIO DM class supporting MDIO buses that are probed as stand-alone devices. Useful in particular for systems that support DM_ETH and have a stand-alone MDIO hardware block shared by multiple Ethernet interfaces. Signed-off-by: NAlex Marginean <alexm.osslist@gmail.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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- 27 5月, 2019 1 次提交
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由 Tom Rini 提交于
Move the main symbol for Freescale Fman Ethernet controller option to Kconfig. Also migrate the CONFIG_SYS_QE_FMAN_FW_IN_xxx macros and rename the SPIFLASH one to follow the same format as all of the others. To do this fully we need to migrate CONFIG_QC, do so. Signed-off-by: NTom Rini <trini@konsulko.com>
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- 03 5月, 2019 1 次提交
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由 Weijie Gao 提交于
Currently mach-mt7620 contains only support for mt7628. To avoid confusion, rename mach-mt7620 to mach-mtmips, which means MediaTek MIPS platforms. MT7620 and MT7628 should be distinguished by SOC_MT7620 and SOC_MT7628 because they do not share the same lowlevel codes. Dependencies of four drivers are changed to SOC_MT7628 as these drivers are only used by MT7628. Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: NStefan Roese <sr@denx.de> Signed-off-by: NWeijie Gao <weijie.gao@mediatek.com>
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- 24 4月, 2019 1 次提交
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由 Shawn Guo 提交于
It adds the driver for HIGMACV300 Ethernet controller found on HiSilicon SoCs like Hi3798CV200. It's based on a downstream U-Boot driver, but quite a lot of code gets rewritten and cleaned up to adopt driver model and PHY API. Signed-off-by: NShawn Guo <shawn.guo@linaro.org> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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- 14 4月, 2019 1 次提交
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由 Lukasz Majewski 提交于
Signed-off-by: NLukasz Majewski <lukma@denx.de> Reviewed-by: NStefan Agner <stefan.agner@toradex.com>
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- 18 2月, 2019 2 次提交
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由 Simon Goldschmidt 提交于
Enable the socfpga specific designware ethernet driver by default for socfpga by implying it when enabling CONFIG_ETH_DESIGNWARE for a MACH_SOCFPGA config. This is required to remove the hacky reset and phy mode handling in arch/arm/mach-socfpga. Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
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由 Simon Goldschmidt 提交于
This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
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- 01 2月, 2019 1 次提交
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由 Horatiu Vultur 提交于
Move file ocelot_switch to mscc_eswitch to prepare to add new net drivers for other MSCC SoCs. Signed-off-by: NHoratiu Vultur <horatiu.vultur@microchip.com>
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- 24 1月, 2019 1 次提交
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由 Gregory CLEMENT 提交于
This patch adds support for the Microsemi Ethernet switch present on Ocelot SoCs. Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com> Reviewed-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
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- 15 1月, 2019 1 次提交
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由 Weijie Gao 提交于
This patch adds ethernet support for Mediatek ARM-based SoCs, including a minimum setup of the integrated switch. Cc: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: NMark Lee <Mark-MC.Lee@mediatek.com> Signed-off-by: NWeijie Gao <weijie.gao@mediatek.com> Tested-By: N"Frank Wunderlich" <frank-w@public-files.de>
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- 19 12月, 2018 2 次提交
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由 Álvaro Fernández Rojas 提交于
Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
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由 Álvaro Fernández Rojas 提交于
Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
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- 06 11月, 2018 3 次提交
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由 Grygorii Strashko 提交于
Add drivers/net/ti/ folder and move all TI's code in this folder for better maintenance. Reviewed-by: NTom Rini <trini@konsulko.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com> Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com>
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由 Cédric Le Goater 提交于
The driver is based on the previous one and the code is only adapted to fit the driver model. The support for the Faraday ftgmac100 controller is the same with MAC and MDIO bus support for RGMII/RMII modes. Configuration is updated to enable compile again. At this stage, the driver compiles but is not yet functional. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NJoel Stanley <joel@jms.id.au> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Stefan Roese 提交于
This patch adds ethernet support for the MIPS based Mediatek MT76xx SoCs (e.g. MT7628 and MT7688), including a minimum setup of the integrated switch. This driver is loosly based on the driver version included in this MediaTek github repository: https://github.com/MediaTek-Labs/linkit-smart-uboot.git Tested on the MT7688 LinkIt smart-gateway and on the Gardena-smart-gateway. Signed-off-by: NStefan Roese <sr@denx.de> Reviewed-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Frank Wunderlich <frankwu@gmx.de> Cc: Weijie Gao <hackpascal@gmail.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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- 25 10月, 2018 1 次提交
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由 Anatolij Gustschin 提交于
Add compatible property and enable the FEC ipg clock when probing on i.MX8X. Add specific function for reading FEC clock rate via clock driver when configuring MII speed register. Allow FEC_MXC selection for i.MX8. Signed-off-by: NAnatolij Gustschin <agust@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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- 16 10月, 2018 1 次提交
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由 Michal Simek 提交于
Xilinx is introducing Versal, an adaptive compute acceleration platform (ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application. The Versal AI Core series has five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm Cortex™-A72 application processors, dual-core Arm Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines optimized for high-precision floating point with low latency. The patch is adding necessary infrastructure in place without enabling platform which is done in separate patch. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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- 18 8月, 2018 1 次提交
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由 Adam Ford 提交于
This converts the following to Kconfig: CONFIG_MII CONFIG_DRIVER_TI_EMAC Signed-off-by: NAdam Ford <aford173@gmail.com> Acked-by: NJagan Teki <jagan@amarulasolutions.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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- 14 8月, 2018 1 次提交
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由 Marek Vasut 提交于
Add wrapper around the designware MAC driver to handle the SoCFPGA specific configuration bits. On Arria10, this is configuration of syscon phy_intf. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
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