- 05 8月, 2015 24 次提交
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由 Simon Glass 提交于
Add a convention that the generic global_data only occupy the bottom 16 bits of the flags word, so that there is less chance of a conflict. At present the x86 flags conflict. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
We should use these constants where possible. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
Fix a typo, improve some comments and add a little more detail in some cases. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
These will be used for efi.h both for U-Boot running as an EFI application and as a payload. They come from Linux 4.1. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
This is currently done for all targets, since 0xff is the default erased value for most flash devices. In some cases this is not what we want (e.g. for EFI images) so provide a command to do a vanilla objcopy. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
Provide the types necessary to relocate 64-bit images. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
In a final attempt to find a console UART this function uses the first first available serial device. However the check for a valid device is inverted. This code is only executed when there is in fact no serial UART, but at present it can fail to reach the panic_str() call in this case, and start trying to use a non-existent UART. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
This function needs to check the list has entries before traversing it. Fix this bug. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
The CFLAGS_REMOVE_<file> feature allows default C compiler flags to be removed for particular files. Add the same feature for assembler, using AFLAGS_REMOVE_<file>. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Peng Fan 提交于
Add '\n' for debug msg. Signed-off-by: NPeng Fan <Peng.Fan@freescale.com> Cc: Tom Rini <trini@konsulko.com> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Simon Glass <sjg@chromium.org> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Masahiro Yamada 提交于
Match the depth of indentation between #ifdef and #endif for better readability. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
Do not print confusing "Board: Unknown" during boot. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
Ignore defconfig and tools/fdtgrep. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
Add PCI IRQ routing information in the board device tree and enable writing PIRQ routing table and MP table. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
Intel Bayley Bay board is a BayTrail based board. Add this board with existing baytrail fsp support. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
This commit adds the microcode blob for BayTrail-I B0 stepping, CPUID signature 30671h. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
BayTrail FSP Gold4 release adds one UPD parameter to control IGD enable/disable. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
On Intel BayTrail SoC, there is a legacy UART (I/O 0x3f8) integrated into the SoC which is enabled by the FSP. Remove the smsc47x superio initialization codes. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
We should not set up kernel screen_info when the vesa parameters are insane, otherwise kernel will panic. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
Add a cpu1 node to the device tree and enable the MP initialization on QEMU targets (i440fx and q35). Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org> Tested-by: NSimon Glass <sjg@chromium.org>
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由 Miao Yan 提交于
When running SMP configuration on QEMU (tcg mode, no kvm), there is a busy loop in start_aps(), calling udelay(), that waits for APs to show up online. However, there is a chance that VCPU1 will be timeout waiting, IOW the secondary VCPUs haven't started their execution yet. This patch adds a 'pause' instruction in __udelay() only for QEMU target, to give other VCPUs a chance to run. When QEMU sees the 'pause' instruction, it will yeild the execution to other CPUs. Signed-off-by: NMiao Yan <yanmiaobest@gmail.com> Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org> Tested-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
Correct two typos and mention how pci bus will be probed. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
On some platforms pci devices behind bridge need to be probed (eg: a pci uart on recent x86 chipset) before relocation. Remove such limitation so that dm pci can be used before relocation. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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- 04 8月, 2015 16 次提交
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由 Vitaly Andrianov 提交于
This patch replaces not existing addr_uboot environment variable by loadaddr at get_uboot_net and burn_uboot_xxx commands. Otherwise these commands are broken. Signed-off-by: NVitaly Andrianov <vitalya@ti.com> Acked-by: NNishanth Menon <nm@ti.com>
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由 Nikhil Badola 提交于
Add USB XHCI support for ls2085rdb platform Signed-off-by: NNikhil Badola <nikhil.badola@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Nikhil Badola 提交于
Add USB XHCI support for ls2085qds platform Signed-off-by: NNikhil Badola <nikhil.badola@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Nikhil Badola 提交于
Define base address of both usb xhci controllers in lsch3 config in the format (IMMR + offset) for LS2085A Signed-off-by: NNikhil Badola <nikhil.badola@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Nikhil Badola 提交于
Define CONFIG_SYS_CACHELINE_SIZE for LS2085A which is required by USB XHCI stack for alignment Signed-off-by: NNikhil Badola <nikhil.badola@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 York Sun 提交于
By default the bstopre value has been set to 0x100, used to be 1/4 value of refint. Modern DDR has increased the refresh time. Adjust to 1/4 of refresh interval dynamically. Individual board can still override this value in board ddr file, or to use auto-precharge. Signed-off-by: NYork Sun <yorksun@freescale.com>
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Signed-off-by: NHoria Geantă <horia.geanta@freescale.com> Acked-by: Ruchika Gupta<ruchika.gupta@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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HW coherency won't work properly for CAAM write transactions if AWCACHE is left to default (POR) value - 4'b0001. It has to be programmed to 4'b0010. For platforms that have HW coherency support: -PPC-based: the update has no effect; CAAM coherency already works due to the IOMMU (PAMU) driver setting the correct memory coherency attributes -ARM-based: the update fixes cache coherency issues, since IOMMU (SMMU) driver is not programmed to behave similar to PAMU Fixes: b9eebfad ("fsl_sec: Add hardware accelerated SHA256 and SHA1") Signed-off-by: NHoria Geantă <horia.geanta@freescale.com> Reviewed-by: NAneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: NMingkai Hu <Mingkai.Hu@freescale.com> Acked-by: Ruchika Gupta<ruchika.gupta@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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Use fdt_setprop_u32() instead of fdt_setprop(). Fixes: 0181937f ("crypto/fsl: Add fixup for crypto node") Signed-off-by: NHoria Geantă <horia.geanta@freescale.com> Reviewed-by: NMingkai Hu <Mingkai.Hu@freescale.com> Acked-by: Ruchika Gupta<ruchika.gupta@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Minghuan Lian 提交于
The patch will initialize PCIe controller on EP mode 1. Setup bar: bar0 32bit 4K for specific configuration bar1 32bit 8K for MSIX bar2 64bit 4K for descriptor of memory bar4 64bit 1M for DMA memory test 2. Setup iATU: iATU inbound 0-3 to map bar transaction to memory address started at CONFIG_SYS_PCI_EP_MEMORY_BASE iATU outbound 0 to map 4G memory space Signed-off-by: NMinghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Minghuan Lian 提交于
PCIe extends device's configuration space to 4k and provides extended capability. The patch adds function to find them. The code is ported from Linux PCIe driver. Signed-off-by: NMinghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Prabhakar Kushwaha 提交于
MC firware version 8.0.0 contains new command flags. This patch contains modifications in FLIB files to support the new command flags. Signed-off-by: NItai Katz <itai.katz@freescale.com> Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Alex Porosanu 提交于
The sampling of the oscillator can be done in multiple modes for generating the entropy value. By default, this is set to von Neumann. This patch changes the sampling to raw data, since it has been discovered that the generated entropy has a better 'quality'. Signed-off-by: NAlex Porosanu <alexandru.porosanu@freescale.com> Acked-by: Ruchika Gupta<ruchika.gupta@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Alex Porosanu 提交于
The entropy delay (the length in system clocks of each entropy sample) for the RNG4 block of CAAM is dependent on the frequency of the SoC. By elaborate methods, it has been determined that a good starting value for all platforms integrating the CAAM IP is 3200. Using a higher value has additional benefit of speeding up the process of instantiating the RNG, since the entropy delay will be increased and instantiation of the RNG state handles will be reattempted by the driver. If the starting value is low, for certain platforms, this can lead to a quite lengthy process. This patch changes the starting value of the length of the entropy sample to 3200 system clocks. In addition to this change, the attempted entropy delay values are now printed on the console upon initialization of the RNG block. Signed-off-by: NAlex Porosanu <alexandru.porosanu@freescale.com> Acked-by: Ruchika Gupta<ruchika.gupta@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Alex Porosanu 提交于
The rtfrqmax & rtfrqmin set the bounds of the expected frequency of the oscillator, when SEC runs at its maximum frequency. For certain platforms (f.i. T2080), the oscillator is very fast and thus if the SEC runs at a lower than normal frequency, the ring oscillator is incorrectly detected as being out of bounds. This patch effectively disables the maximum frequency check, by setting a high enough maximum allowable frequency for the oscillator. The reasoning behind this is that usually a broken oscillator will run too slow (i.e. not run at all) rather than run too fast. Signed-off-by: NAlex Porosanu <alexandru.porosanu@freescale.com> Acked-by: Ruchika Gupta<ruchika.gupta@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Alison Wang 提交于
To improve eTSEC performance on LS1021A Rev2.0, snooping of all transmit frames from memory and all transmit BD memory accesses in enabled. Signed-off-by: NAlison Wang <alison.wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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