Add ehci_get_port_speed() and ehci_set_usbmode() weak functions
for platform driver to support new chip.
Signed-off-by: NJim Lin <jilin@nvidia.com>

With the u-boot-with-spl.bin rule calling $(OBJCOPY) with
CONFIG_SPL_PAD_TO, and CONFIG_SPL_PAD_TO defaulting to
CONFIG_SPL_MAX_SIZE we cannot use math here, so set it to 4096 rather
than 4 * 1024.
Signed-off-by: NTom Rini <trini@ti.com>

The Hydra and Superhydra (P3041DS, P5020DS, and P5040DS) boards have a
second USB port that can be configured in either host, peripheral (aka
device), or OTG (on-the-go) mode.  When configured in host mode, if
the port is connected to another USB host, damage to the board can
occur.

To avoid this, we change the default setting to peripheral mode.  Ideally,
we'd set it to OTG mode, but currently there is no OTG support for
these boards.

Setting the hwconfig variable will also update the device tree, and so
Linux will configure the port for peripheral mode as well.
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: NTimur Tabi <timur@tabi.org>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

When P1021RDB-PC reboot system, the board will hung at uboot DDR
configuration. For P1021RDB-PC DDR reset pin is multiplex with
QE, so uboot will reserve this pin for QE and skip DDR reset.
Other platforms without QE will do this reset. This patch adds
a slight code to reset DDR chip by QE CE_PB8 pin for NAND and
NOR FLASH boot. For booting from SPI FALSH and SD card, it
seems possible to use the rom on chip to write to the GPIO
pins before configuring the DDR.
Signed-off-by: NXu Jiucheng <B37781@freescale.com>
Signed-off-by: NXie Xiaobo <X.Xie@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Extending LIODN offset range from 1-5 to 1-10
While using a qman portal with a higher index the LIODN offset
is incorrectly set, thus extending the range of offsets covers
all 10 qman portals
Signed-off-by: NCristian Sovaiala <cristian.sovaiala@freescale.com>
Acked-by: NHaiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Erratum DDR_A003 applies to P5020, P3041, P4080, P3060, P2041, P5040.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Change flexcan compatible string from "fsl,flexcan-v1.0"
to "fsl,p1010-flexcan" to match the device tree.
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Only some chips have four SerDes banks, so don't define lanes for a bank
that doesn't exist.
Signed-off-by: NTimur Tabi <timur@tabi.org>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Resolve P1020 second USB controller multiplexing with eLBC
         - mandatory to mention USB2 in hwconfig string to select it
           over eLBC, otherwise USB2 node is removed
         - works only for SPI and SD boot
Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
Signed-off-by: NZhicheng Fan <B32736@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

There could be scenarios where the user would like to manually(via JTAG)
configure the DDR/L2SRAM and load the bootloader binary onto DDR/L2SRAM.
This document explains thse usecases and the detailed explanation of what needs
to be done to use it.

Most of the code from CONFIG_SYS_RAMBOOT will be used except for small changes
of CCSRBAR etc.

The changes are not very large, but it is good to document them so that user
can get it working at once.
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

As per Errata list of BSC9131 and BSC9132, IFC Errata A003399 is no more
valid. So donot compile its workaround.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

cpu.c:288:2:
warning: implicit declaration of function 'reset_85xx_watchdog'
[-Wimplicit-function-declaration]
Signed-off-by: NHorst Kronstorfer <hkronsto@frequentis.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

On P204x/P304x/P50x0 Rev1.0, USB transmit will result in false internal
multi-bit ECC errors, which has impact on performance, so software should
disable all ECC reporting from USB1 and USB2.

In formal release document, the errata number should be USB14 instead of USB138.
Signed-off-by: Nxulei <Lei.Xu@freescale.com>
Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
Signed-off-by: Nxulei <B33228@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Add the tlb entries based on the configuration of the SRIO interfaces.
Every SRIO interface has 256M space:

	#define CONFIG_SYS_SRIO1_MEM_VIRT   0xa0000000
	#define CONFIG_SYS_SRIO1_MEM_PHYS   0xc20000000ull

	#define CONFIG_SYS_SRIO2_MEM_VIRT   0xb0000000
	#define CONFIG_SYS_SRIO2_MEM_PHYS   0xc30000000ull
Signed-off-by: NLiu Gang <Gang.Liu@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Some legacy RGMII phys don't have in band signaling for the
speed information. so set the RGMII MAC mode according to
the speed got from PHY.
Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com>
Reported-by: NJohn Traill <john.traill@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

For T4/B4, the clockgen node compatible string is updated to version 2.
Add clock-frequency setting for this new version.
Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Per the latest errata updated, B4860/B4420 Rev 1.0 has also
errata A-005871, so adding define A-005871 for B4 SoCs.
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

B4420/B4860 PCIE can not work because of the wrong definition of
the PCIE register offset in the file:
	arch/powerpc/include/asm/immap_85xx.h

Add the judgement of B4420/B4860 to make the register offset to:
	#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET         0x200000
Signed-off-by: NLiu Gang <Gang.Liu@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Add defines needed to access NAND, remove second flash bank that is
actually connected to NAND.

Add nand booting support for P1022DS with hardcoded DDR config using
SPL framework from 2011
Signed-off-by: NMatthew McClintock <msm@freescale.com>
Signed-off-by: NJerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: NJiang Yutang <b14898@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Set the device tree property associated with the mpic source
frequency. The frequency is used for mpic timer.
Signed-off-by: NWang Dongsheng <dongsheng.wang@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

The 'fsl,pme-rev1' and 'fsl-pme-rev2' properties have been added to the
pme portal node. This is required for software to determine which version
of PME hardware is present and take appropriate actions.
These properties are a direct reflection of the corresponding ccsr pme
register value.

Also removed unnecessary static global variables.
Signed-off-by: NJeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

For linux 3.x, the size of each item in interrupt-map property is 9 not 7.
Don't use the static value and calculate the size with following cells:
	PCI #address-cells, PCI #interrupt-cells,
	PIC address, PIC #address-cells, PIC #interrupt-cells.
Signed-off-by: NBin Jiang <bin.jiang@windriver.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

The changes to a3m071/a4m2k in summary are:
- Enable CAN1 on I2C in GPS Port Configuration
- Enable SPI on PSC2
- Activate network console
- New flash partitioning
- Fix some typos
- Pass host name to Linux
- Change rootfs to squashfs,jffs2
- Enable UBI/UBIFS support
- Enable FIT support
Signed-off-by: NStefan Roese <sr@denx.de>

The v2013.04 release has this patch set included:

5cb48582 "Add architecture-specific global data"

With this, the global_data struct is now common and new variables
have been added. Resulting in a bigger struct. Unfortunately the
currently allocated 128 bytes are just a bit too small for this
new struct.

This patch now uses the automatically generated struct size instead to
not run into this problem again.

Please note that this problem might hit some other platforms which
currently reserve a tight space of 128 bytes for the global_data
struct!
Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NStefan Roese <sr@denx.de>

The prt_mpc512x_clks() function isn't referenced
anywhere and its prototype is wrong. Remove it.
Signed-off-by: NAnatolij Gustschin <agust@denx.de>

Cc: Sricharan R <r.sricharan@ti.com>
Signed-off-by: NTom Rini <trini@ti.com>

The redundancy related defines are only correct for NAND, so guard all
of that area with CONFIG_ENV_IS_IN_NAND

Cc: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NTom Rini <trini@ti.com>

This patch add support for storing the environment redundant on
mmc devices. Substantially it re-uses the logic from the NAND implementation,
that means using an incremental counter for marking newer data.
Signed-off-by: NMichael Heimpold <mhei@heimpold.de>

Delete all occurrences of hang() and provide a generic function.
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
Acked-by: NAlbert ARIBAUD <albert.u.boot@aribaud.net>
[trini: Modify check around puts() in hang.c slightly]
Signed-off-by: NTom Rini <trini@ti.com>

In order to use the generic hang() later on pull libgeneric in SPL.
This has no impact on the SPL size.
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

In order to use the generic hang() later on pull libgeneric in SPL.
This has no impact on the SPL size.
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

Make nios2's board.c checkpatch clean.
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

Make microblaze's board.c checkpatch clean.
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
Reviewed-by: NMichal Simek <monstr@monstr.eu>

log2 of the device block size serves as the shift value used to calculate
the block number to read in file systems when implementing avaiable block
sizes.
It is needed quite often in file systems thus it is pre-calculated and
stored in the block device descriptor.
Signed-off-by: NEgbert Eich <eich@suse.com>

Bugfix:
Here at this place we need the fat size in sectors not bytes.
This was found during code review when adding support for storage
devices with blocksizes != 512.
Signed-off-by: NEgbert Eich <eich@suse.com>

For ISO we check the block size of the device if this is != the CD sector
size we assume that the device has no ISO partition.
Signed-off-by: NEgbert Eich <eich@suse.com>