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  1. 08 10月, 2009 2 次提交
    • J
      relocation: Do not relocate NULL pointers. · afc3ba0f
      由 Joakim Tjernlund 提交于 
      NULL is an absolute value and should not be relocated.
After this correction code like:
 void weak_fun(void) __attribute__((weak));
 printf("weak_fun:%p\n", weak_fun);
will still print null after relocation.
Signed-off-by: NJoakim Tjernlund <Joakim.Tjernlund@transmode.se>
      afc3ba0f
    • P
      85xx: Ensure BSS segment isn't linked at address 0 · 3beb40c2
      由 Peter Tyser 提交于 
      When U-Boot is relocated from flash to RAM pointers are modified
accordingly.  However, pointers initialzed with NULL values should not
be modified so that they maintain their intended NULL value.  If the
BSS segment is linked at address 0 its address will not be
updated as necessary during relocation.

This is a temporary workaround.  The end goal is to add support to
U-Boot to dynamically locate the BSS at an arbitrary address at
runtime.  When the ability to fixup the BSS inteligently is
added, this workaround can be removed and the 85xx link script
can put the BSS at a fixed address at link time.
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
      3beb40c2
  3. 03 10月, 2009 14 次提交
  5. 01 10月, 2009 7 次提交
  7. 30 9月, 2009 6 次提交
    • K
      ppc/85xx: get_law_entry isn't used in CONFIG_NAND_SPL · 24b17d8a
      由 Kumar Gala 提交于 
      Don't include get_law_entry as part of the NAND_SPL build since the
code isnt used.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      24b17d8a
    • M
      Add README.mpc8536ds · 693a048d
      由 Mingkai Hu 提交于 
      Add boot from NAND/eSDHC/eSPI description
Signed-off-by: NMingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      693a048d
    • M
      On-chip ROM boot: MPC8536DS support · e40ac487
      由 Mingkai Hu 提交于 
      The MPC8536E is capable of booting from the on-chip ROM - boot from
eSDHC and boot from eSPI. When power on, the porcessor excutes the
ROM code to initialize the eSPI/eSDHC controller, and loads the mian
U-Boot image from the memory device that interfaced to the controller,
such as the SDCard or SPI EEPROM, to the target memory, e.g. SDRAM or
L2SRAM, then boot from it.

The memory device should contain a specific data structure with control
word and config word at the fixed address. The config word direct the
process how to config the memory device, and the control word direct
the processor where to find the image on the memory device, or where
copy the main image to. The user can use any method to store the data
structure to the memory device, only if store it on the assigned address.

The on-chip ROM code will map the whole 4GB address space by setting
entry0 in the TLB1, so the main image need to switch to Address space 1
to disable this mapping and map the address space again.

This patch implements loading the mian U-Boot image into L2SRAM, so
the image can configure the system memory by using SPD EEPROM.
Signed-off-by: NMingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      e40ac487
    • M
      NAND boot: MPC8536DS support · 9a1a0aed
      由 Mingkai Hu 提交于 
      MPC8536E can support booting from NAND flash which uses the
image u-boot-nand.bin. This image contains two parts: a 4K
NAND loader and a main U-Boot image. The former is appended
to the latter to produce u-boot-nand.bin. The 4K NAND loader
includes the corresponding nand_spl directory, along with the
code twisted by CONFIG_NAND_SPL. The main U-Boot image just
like a general U-Boot image except the parts that included by
CONFIG_SYS_RAMBOOT.

When power on, eLBC will automatically load from bank 0 the
4K NAND loader into the FCM buffer RAM where CPU can execute
the boot code directly. In the first stage, the NAND loader
copies itself to RAM or L2SRAM to free up the FCM buffer RAM,
then loads the main image from NAND flash to RAM or L2SRAM
and boot from it.

This patch implements the NAND loader to load the main image
into L2SRAM, so the main image can configure the RAM by using
SPD EEPROM. In the first stage, the NAND loader copies itself
to the second to last 4K address space, and uses the last 4K
address space as the initial RAM for stack.

Obviously, the size of L2SRAM shouldn't be less than the size
of the image used. If so, the workaround is to generate another
image that includes the code to configure the RAM by SPD and
load it to L2SRAM first, then relocate the main image to RAM
to boot up.
Signed-off-by: NMingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      9a1a0aed
    • M
      mpc8536: fix board config file line length · 07355700
      由 Mingkai Hu 提交于 
      Signed-off-by: NMingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      07355700
    • P
      sbc8548: reclaim wasted sector in boot flash · dd9ca98f
      由 Paul Gortmaker 提交于 
      By nature of being based off the MPC8548CDS board, this
board inherited an ENV_SIZE setting of 256k.  But since
it has a smaller flash device (8MB soldered on), it has
a native sector size of 128k, and hence the ENV_SIZE was
causing 2 sectors to be used for the environment.

By removing the unused sector, we can push TEXT_BASE up
closer to the end of address space and reclaim that
sector for any other application.  This also fixes the
mismatch between TEXT_BASE and MONITOR_LEN reported by
Kumar earlier.

Since this board also supports the ability to boot off
the 64MB SODIMM flash, this change is forward looking
with that in mind; i.e. the settings for MONITOR_LEN
and ENV_SIZE will work when the 512k sectors of the
SODIMM flash are used for alternate boot in the future.
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      dd9ca98f
  9. 29 9月, 2009 4 次提交
  11. 28 9月, 2009 7 次提交