Fix a bug introduced by this patch
powerpc/mpc85xx: Temporary fix for spin table backward compatibility

Should have checked both CONFIG_PPC_SPINTABLE_COMPATIBLE and CONFIG_MP in
cpu_init.c.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

The documented work-around for P4080 erratum SERDES-9 has been updated.
It is now compatible with the work-around for erratum A-4580.

This requires adding a few bitfield macros for the BnTTLCRy0 register.
Signed-off-by: NTimur Tabi <timur@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Due to SerDes configuration error, if we set the PCI-e controller link width
as x8 in RCW and add a narrower width(such as x4, x2 or x1) PCI-e device to
PCI-e slot, it fails to train down to the PCI-e device's link width. According
to p4080ds errata PCIe-A003, we reset the PCI-e controller link width to x4 in
u-boot. Then it can train down to x2 or x1 width to make the PCI-e link between
RC and EP.
Signed-off-by: NYuanquan Chen <B41889@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

board configuration file is included before asm/config_mpc85xx.h.
however, CONFIG_FSL_SATA_V2 is defined in asm/config_mpc85xx.h.
it will never take effective in the board configuration file for
this kind of code :

 #ifdef CONFIG_FSL_SATA_V2
 ...
 #endif

To solve this problem, move CONFIG_FSL_SATA_V2 to board
configuration header file.

This patch reverts Timur's
commit:3e0529f7Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

The work-around for erratum A-004580 ("Internal tracking loop can falsely
lock causing unrecoverable bit errors") is implemented via the PBI
(pre-boot initialization code, typically attached to the RCW binary).
This is because the work-around is easier to implement in PBI than in
U-Boot itself.

It is still useful, however, for the 'errata' command to tell us whether
the work-around has been applied.  For A-004580, we can do this by verifying
that the values in the specific registers that the work-around says to
update.

This change requires access to the SerDes lane sub-structure in
serdes_corenet_t, so we make it a named struct.
Signed-off-by: NTimur Tabi <timur@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

by moving compat_strlist into the .bss section.

0xfe004d80 fdt_fixup_crypto_node [u-boot]:		264
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Once u-boot sets the spin table to cache-enabled memory, old kernel which
uses cache-inhibit mapping without coherence will not work properly. We
use this temporary fix until kernel has updated its spin table code.
For now this fix is activated by default. To disable this fix for new
kernel, set environmental variable "spin_table_compat=no". After kernel
has updated spin table code, this default shall be changed.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

P2041RDB uses common corenet TLB and LAW. However it doesn't have promjet
connector. It is necessary to use the same base address for correct LAW
address. An offset is added for NOR flash.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Single rank UDIMM timing has been verified with HMT325U7BFR8C-H9 for speed
800, 900, 1000, 1200, 1300MT/s.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

The work-around for erratum A-004849 ("CoreNet fabric (CCF) can exhibit a
deadlock under certain traffic patterns causing the system to hang") is
implemented via the PBI (pre-boot initialization code, typically attached
to the RCW binary).  This is because the work-around is easier to implement
in PBI than in U-Boot itself.

It is still useful, however, for the 'errata' command to tell us whether
the work-around has been applied.  For A-004849, we can do this by verifying
that the values in the specific registers that the work-around says to
update.
Signed-off-by: NTimur Tabi <timur@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

The P5040DS reference board (a.k.a "Superhydra") is an enhanced version of
P3041DS/P5020DS ("Hydra") reference board.
Signed-off-by: NTimur Tabi <timur@freescale.com>
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

The P5040 has an e5500 core, so CONFIG_SYS_PPC64 should be defined in
config_mpc85xx.h.  This macro was absent in the initial P5040 patch because
it crossed paths with the patch that introduced the macro.

Also delete CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC, since it's not used in the
upstream U-Boot.  It's a holdover from the SDK.
Signed-off-by: NTimur Tabi <timur@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Move FMAN microcude from 0xEF000000 to 0xEFF40000 to free up the beginning
of this virtual bank so that this bank can store RCW or be used together
with other banks to store large images.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

There were a number of shared files that were using
CONFIG_SYS_MPC85xx_DDR_ADDR, or CONFIG_SYS_MPC86xx_DDR_ADDR, and
several variants (DDR2, DDR3). A recent patchset added
85xx-specific ones to code which was used by 86xx systems.
After reviewing places where these constants were used, and
noting that the type definitions of the pointers assigned to
point to those addresses were the same, the cleanest approach
to fixing this problem was to unify the namespace for the
85xx, 83xx, and 86xx DDR address definitions.

This patch does:

s/CONFIG_SYS_MPC8.xx_DDR/CONFIG_SYS_MPC8xxx_DDR/g

All 85xx, 86xx, and 83xx have been built with this change.
Signed-off-by: NAndy Fleming <afleming@freescale.com>
Tested-by: NAndy Fleming <afleming@freescale.com>
Acked-by: NKim Phillips <kim.phillips@freescale.com>

usbdescriptors.h conflicts with linux/usb/ch9.h
Remove it.
Signed-off-by: NPantelis Antoniou <panto@antoniou-consulting.com>

This patch adds a NAND Flash torture feature, which is useful as a block stress
test to determine if a block is still good and reliable (or should be marked as
bad), e.g. after a write error.

This code is ported from mtd-utils' lib/libmtd.c.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Scott Wood <scottwood@freescale.com>
[scottwood@freescale.com: removed unnec. ifdef and unwrapped error strings]
Signed-off-by: NScott Wood <scottwood@freescale.com>

NAND Flash is erased by blocks, not by pages.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Scott Wood <scottwood@freescale.com>

This patch cleans up nand_util.c:
 - Fix tabs.
 - Fix typos.
 - Remove space character before opening parenthesis in function calls.
 - Fix comments.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Scott Wood <scottwood@freescale.com>

Use a flag instead of a hard-coded macro so that sub-page reads can be
enabled in other cases (such as on-die ecc).

This is the same as a5ff4f102937a3492bca4a9ff0c341d78813414c in Linux
Signed-off-by: NJoe Hershberger <joe.hershberger@ni.com>

IFC-1.1.0 uses 28nm techenology for SRAM. This tech has known limitaion for
SRAM i.e. "byte select" is not supported. Hence Read Modify Write is
implemented in IFC for any "system side write" into sram buffer. Reading an
uninitialized memory results in ECC Error from sram wrapper.

Hence we must initialize/prefill SRAM buffer by any data before writing
anything in SRAM from system side. To initialize SRAM user can use "READID"
NAND command with read bytes equal to SRAM size. It will be a one time
activity post boot
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
[scottwood@freescale.com: fix fsl_ifc_sram_init prototype]
Signed-off-by: NScott Wood <scottwood@freescale.com>

Reference nand monitor commands in U-Boot README
Signed-off-by: NKarl O. Pinc <kop@meme.com>

These controllers can only do hardware ECC on full page transfers.
Signed-off-by: NScott Wood <scottwood@freescale.com>

This allows DDR configuration to be deferred to the final U-Boot image,
which is able to make use of SPD data.  The SPL itself cannot use SPD due
to code size constraints.  It previously used fixed register values for
DDR configuration, and those values did not work on the p2020rdb-pca
board I tested with.  It's possible that different revisions of the board
require different settings.  Using SPD eliminates that problem.
Signed-off-by: NScott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>

- Sort by address, and fix column alignment

- Don't label things as localbus that aren't.  Instead, put chipselect
  info at the end of the description for localbus windows.  Note that
  NAND/NOR have their chipselects swapped when booting from NAND, and CS2
  can be either PMC or VSC7385 depending on hwconfig.

- Shrink NAND to the 32K that's actually mapped in the localbus

- Assign an address and size to L2 SRAM.  Remove the similarly named
  but unintelligible "L2 SDRAM(REV.)".

- Remove the untrue comment about L1 stack being mapped with TLB0.
Signed-off-by: NScott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>

Signed-off-by: NScott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>

Document parameters used for specifying the NAND image to be loaded.

Also fix the definition of CONFIG_SPL_NAND_SIMPLE -- it's only
nand_spl_simple.c, not the entire nand directory.  The word "simple" is
there for a reason.  :-)
Signed-off-by: NScott Wood <scottwood@freescale.com>
---
v2: updated for makefile changes earlier in patchset

Some small SPLs do not use nand_base.c, and a subset of those also
require a special driver.  Some SPLs need software ECC but others can't
fit it.

All existing boards that specify CONFIG_SPL_NAND_SUPPORT have these
symbols added to preserve existing behavior.
Signed-off-by: NScott Wood <scottwood@freescale.com>
--
v2: use positive logic for including bits of NAND, rather than
a MINIMAL symbol that excludes things.

Introduces CONFIG_SPL_RELOC_TEXT_BASE and CONFIG_SPL_RELOC_STACK.
Signed-off-by: NScott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>

Update CONFIG_RAMBOOT and CONFIG_NAND_SPL references to accept CONFIG_SPL
and CONFIG_SPL_BUILD, respectively.  CONFIG_NAND_SPL can be removed once
the last mpc85xx nand_spl target is gone.

CONFIG_RAMBOOT will need to remain for other use cases, but it doesn't
seem right to overload it for meaning SPL as well as nand_spl does.  Even
if it's somewhat appropriate for the main u-boot, the SPL itself isn't
(necessarily) ramboot, and we don't have separate configs for SPL and
main u-boot.  It was also inconsistent, as other platforms such as
mpc83xx didn't use CONFIG_RAMBOOT in this way.
Signed-off-by: NScott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>

cpu_init_nand.c is renamed to spl_minimal.c as it is not really NAND-specific.
Signed-off-by: NScott Wood <scottwood@freescale.com>
---
v2: factor out START, and change cpu_init_nand.c to spl_minimal.c
Cc: Andy Fleming <afleming@freescale.com>

A subsequent patch will conditionalize some of the files that are
currently unconditional.
Signed-off-by: NScott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>

There is nothing really NAND-specific about this file.
Signed-off-by: NScott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>

The toplevel makefile hardcodes this stuff, so spl/Makefile needs to as well.
Signed-off-by: NScott Wood <scottwood@freescale.com>

It applies to non-Freescale 85xx boards as well as Freescale boards,
so it doesn't belong in board/freescale.  Plus, it needs to come out
of nand_spl if it's to be used by the new SPL.
Signed-off-by: NScott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>

It's arch code and not a driver, so move it where it belongs.  When it
originally went into drivers/misc there was no 8xxx CPU directory.

This will make new-SPL support a little easier since we can keep the CPU
stuff together and not need to pull stuff in from drivers/misc.
Signed-off-by: NScott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>

In the RAMBOOT/SPL case we were creating a TLB entry starting at
CONFIG_SYS_MONITOR_BASE, and just hoping that the base was properly
aligned for the TLB entry size.  This turned out to not be the case
with NAND SPL because the main U-Boot starts at an offset into the image
in order to skip the SPL itself.

Fix the TLB entry to always start at a proper alignment.  We still assume that
CONFIG_SYS_MONITOR_BASE doesn't start immediately before a large-page boundary
thus requiring multiple TLB entries.
Signed-off-by: NScott Wood <scottwood@frescale.com>
Cc: Andy Fleming <afleming@freescale.com>

This was introduced by commit 24461519, but it
fails in a minimal SPL build where the only thing in arch/powerpc/lib is
cache.c, which apparently doesn't generate any fixup records.

The problem is reported to occur with GCC 3.x, so insist on GCC 4.0 or newer.
Patterned after checkthumb as suggested by Tom Rini.
Signed-off-by: NScott Wood <scottwood@freescale.com>
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Tom Rini <trini@ti.com>
--
v2: test gcc version instead of testing nothing

Currently the SPL target is specified in a CPU-specific makefile
fragment.  While some targets may need something more complicated than a
simple target name, targets which don't need this shouldn't have to provide a makefile fragment just for this.
Signed-off-by: NScott Wood <scottwood@freescale.com>
---
v2: Removed default target as it's been pointed out to me how existing platforms
cause the SPL to be built.

Signed-off-by: NScott Wood <scottwood@freescale.com>