Signed-off-by: NTom Rini <trini@ti.com>

This patch add the OMAP34XX_UART4 memory address
Signed-off-by: NMichael Trimarchi <michael@amarulasolutions.com>

Certain EFUSE settings were recommended for the first
four lots of OMAP5 ES1.0 silicon. These are not applicable
for OMAP5 ES2.0 and DRA7 silicon. So removing these EFUSE settings.
Reported-by: NGriffis, Brad <bgriffis@ti.com>
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

The evm has a SATA port. Enable SATA configuration and
inititialize the SATA controller.
Signed-off-by: NRoger Quadros <rogerq@ti.com>

Adds the necessary PRCM and Control register information for
SATA on DRA7xx.
Signed-off-by: NRoger Quadros <rogerq@ti.com>

The uevm has a SATA port. Inititialize the SATA controller.
Signed-off-by: NRoger Quadros <rogerq@ti.com>

Add platform glue logic for the SATA controller.
Signed-off-by: NRoger Quadros <rogerq@ti.com>

Adds the necessary PRCM and Control register information for
SATA on OMAP5.
Signed-off-by: NRoger Quadros <rogerq@ti.com>

Pipe3 PHY is used by SATA, USB3 and PCIe modules. This is
a driver for the Pipe3 PHY.
Signed-off-by: NRoger Quadros <rogerq@ti.com>

Align the ATA ID buffer to the cache-line boundary. This gets rid
of the below error mesages on ARM v7 platforms.

 scanning bus for devices...
 ERROR: v7_dcache_inval_range - start address is not aligned - 0xfee48618
 ERROR: v7_dcache_inval_range - stop address is not aligned - 0xfee48818

CC: Aneesh V <aneesh@ti.com>
Signed-off-by: NRoger Quadros <rogerq@ti.com>

If malloc() fails, we don't want to continue in ahci_init() and
ahci_init_one(). Also print a more informative error message on
malloc() failures.

CC: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: NRoger Quadros <rogerq@ti.com>

When core power domain hits oswr, then DDR3 memories does not come back
while resuming. This is because when EMIF registers are lost, then the
controller takes care of copying the values from the shadow registers.
If the shadow registers are not updated with the right values, then this
results in incorrect settings while resuming. So updating the shadow registers
with the corresponding status registers here during the boot.
Signed-off-by: NSricharan R <r.sricharan@ti.com>

Currently the DDR3 memory on DRA7 ES1.0 evm board is enabled using
software leveling. This was done since hardware leveling was not
working. Now that the right sequence to do hw leveling is identified,
use it. This is required for EMIF clockdomain to idle and come back
during lowpower usecases.
Signed-off-by: NSricharan R <r.sricharan@ti.com>

A generic is_dra7xx cpu check is useful for grouping
all the revisions under that. This is used in the
subsequent patches.
Signed-off-by: NSricharan R <r.sricharan@ti.com>

Based on the definitive guide to EMIF configuration[1] certain registers
that we have been modifying (and are documented registers) should be
left in their reset values rather than modified.  This has been tested
on AM335x GP EVM and Beaglebone White.

[1]: http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips
Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Cc: Javier Martinez Canillas <javier@dowhile0.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Lars Poeschel <poeschel@lemonage.de>
Signed-off-by: NTom Rini <trini@ti.com>
Tested-by: NMatt Porter <matt.porter@linaro.org>

Added chip type detection and twl6032
support in the battery control
and charge functions.

Based on Balaji T K <balajitk@ti.com> patches for TI u-boot.
Signed-off-by: NOleg Kosheliev <oleg.kosheliev@ti.com>

The data struct is used to support different
PMIC chip types. It contains the chip type and
the data (e.g. registers addresses, adc multiplier)
which is different for twl6030 and twl6032.
Replaced some hardcoded values with the
structure vars.

Based on Balaji T K <balajitk@ti.com> patches for TI u-boot.
Signed-off-by: NOleg Kosheliev <oleg.kosheliev@ti.com>

The struct incorrectly referenced SMPS1 for all three power
domains. Fixed this by using SMPS2 and SMPS5 as appropriate.

Add some comments and choose voltage values that correspond
to voltage selection codes.
Signed-off-by: NLubomir Popov <l-popov@ti.com>

Phytec sells revision or version 3 of pcm051. It is labeled 1358.3 on
the board. The difference for u-boot is that is has other DDR3 RAM on it:
1 x MT41K256M16HA125E instead of 2 x MT41J256M8HX15E on revisions 1 and
2. Both configurations are 512 MiB.
Configure your u-boot build with pcm051_rev3 for the new RAM and
pcm051_rev1 for the old RAM configuration. Board revision 2 has to use
pcm051_rev1 also.
Signed-off-by: NLars Poeschel <poeschel@lemonage.de>

Add support for the 16 bits pca9555 i2c to gpio extender featured
by the SB-T335 baseboard.
Signed-off-by: NIlya Ledvich <ilya@compulab.co.il>
Signed-off-by: NIgor Grinberg <grinberg@compulab.co.il>

Add support for status LED. Use the STATUS_LED APIs for indicating a
boot progress.
Signed-off-by: NIlya Ledvich <ilya@compulab.co.il>
Signed-off-by: NIgor Grinberg <grinberg@compulab.co.il>

Add cm_t335 board directory, config file. Enable build.
Signed-off-by: NIlya Ledvich <ilya@compulab.co.il>
Signed-off-by: NIgor Grinberg <grinberg@compulab.co.il>
[trini: Adapt Makefile]
Signed-off-by: NTom Rini <trini@ti.com>

Adding Freeze Controller driver. All HPS IOs need to be
in freeze state during pin mux or IO buffer configuration.
It is to avoid any glitch which might happen
during the configuration from propagating to external devices.
Signed-off-by: NChin Liang See <clsee@altera.com>
Cc: Wolfgang Denk <wd@denx.de>
CC: Pavel Machek <pavel@denx.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>

* remove mature defines from board config
Signed-off-by: NJens Scharsig (BuS Elektronik) <esw@bus-elektronik.de>
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

In config_cmd_default.h, it will use CONFIG_SYS_NO_FLASH to decide
whether include CONFIG_CMD_FLASH and CONFIG_CMD_IMLS. So, if the
CONFIG_SYS_NO_FLASH defined later than include/config_cmd_default.h,
These two commands will be included always.

So move CONFIG_SYS_NO_FLASH definition to proper position.
Signed-off-by: NBo Shen <voice.shen@atmel.com>
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

add common phy reset code into a common function.
Signed-off-by: NHeiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Bo Shen <voice.shen@atmel.com>
Cc: Jens Scharsig <esw@bus-elektronik.de>
Cc: Sergey Lapin <slapin@ossfans.org>
Cc: Stelian Pop <stelian@popies.net>
Cc: Albin Tonnerre <albin.tonnerre@free-electrons.com>
Cc: Eric Benard <eric@eukrea.com>
Cc: Markus Hubig <mhubig@imko.de>
Acked-by: NJens Scharsig (BuS Elektronik) <esw@bus-elektronik.de>
Tested-by: NJens Scharsig (BuS Elektronik) <esw@bus-elektronik.de>
Tested-by: NBo Shen <voice.shen@atmel.com>
Acked-by: NBo Shen <voice.shen@atmel.com>
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

Enable Atmel sama5d3xek boart spl boot support, which can load u-boot
from SD card with FAT file system.
Signed-off-by: NBo Shen <voice.shen@atmel.com>
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

The MPDDRC supports different type of SDRAM
This patch add ddr2 initialization function
Signed-off-by: NBo Shen <voice.shen@atmel.com>
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

Enable the PIO peripherals early than other peripherals.
Signed-off-by: NBo Shen <voice.shen@atmel.com>
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

The offset of MULA field in PLLA register in sama5d3 is 18,
and the length only 7 bits.
Signed-off-by: NBo Shen <voice.shen@atmel.com>
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

Correct the error define of DIV.
Signed-off-by: NBo Shen <voice.shen@atmel.com>
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

The PLLADIV2 bit is not defined in at91sam9261 SoC, so remove it.
Signed-off-by: NBo Shen <voice.shen@atmel.com>
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

As the DBGU and PIT has its own ID on sama5d3 SoC, while not share
with SYS ID. So, correct them.
Signed-off-by: NBo Shen <voice.shen@atmel.com>
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

The SAMA5D36 chip is the superset product of SAMA5D3x family.

For detail information please refer to:
  http://www.atmel.com/Microsite/sama5d3/default.aspxSigned-off-by: NJosh Wu <josh.wu@atmel.com>
Acked-by: NBo Shen <voice.shen@atmel.com>
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
Acked-by: NBo Shen <voice.shen@atmel.com>