- 19 8月, 2014 3 次提交
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由 Stephen Warren 提交于
In at least Tegra124, the Tegra memory controller (MC) has a register that controls the memory size. Read this to determine the memory size rather than requiring this to be redundantly encoded into the ODMDATA. This way, changes to the BCT (i.e. MC configuration) automatically updated SW's view of the memory size, without requiring manual changes to the ODMDATA. Future work potentially required: * Clip the memory size to architectural limits; U-Boot probably doesn't and won't support either LPAE or Tegra's "swiss cheese" memory layout, at least one of which would be required for >2GB RAM. * Subtract out any carveout required by firmware on future SoCs. Based-on-work-by: NTom Warren <twarren@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Stephen Warren 提交于
Enable DFU protocol support (via the "dfu" command) on Tegra boards where USB device/gadget mode is enabled. Note that for DFU to operate correctly on Tegra, we still need some DFU fixes/enhancements that are going through the DFU -> USB trees. However, the code builds just fine without those changes, and applying this patch now will allow both sets of patches to meet in the main U-Boot tree much more quickly. In order to run test/dfu/dfu_gadget_test.sh, you would need to add the following to the board configuration: CONFIG_EXT4_WRITE CONFIG_CMD_EXT4_WRITE However, I haven't enabled those here, since I believe the main use-case for DFU on Tegra is raw flash writing, rather than filesystem access, so we don't need the additional code-size hit. However, I could be persuaded otherwise! We should probably add a separate test script for raw flash access. Signed-off-by: NStephen Warren <swarren@nvidia.com> Acked-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Bryan Wu 提交于
On Tegra114 and Tegra124 platforms, certain display-related registers cannot be accessed unless the VPR registers are programmed. For bootloader, we probably don't care about VPR, so we disable it (which counts as programming it, and allows those display-related registers to be accessed). This patch is based on the commit 5f499646c83ba08079f3fdff6591f638a0ce4c0c in Chromium OS U-Boot project. Signed-off-by: NAndrew Chew <achew@nvidia.com> Signed-off-by: NJimmy Zhang <jimmzhang@nvidia.com> Signed-off-by: NBryan Wu <pengw@nvidia.com> [acourbot: ensure write went through, vpr.c style changes] Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com> Reviewed-by: NStephen Warren <swarren@nvidia.com> Cc: Tom Warren <TWarren@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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- 09 8月, 2014 1 次提交
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由 Albert ARIBAUD 提交于
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- 06 8月, 2014 13 次提交
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由 Tom Rini 提交于
Signed-off-by: NTom Rini <trini@ti.com>
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由 Andy Fleming 提交于
Messages to afleming@freescale.com now bounce, and should be directed to my personal address at afleming@gmail.com Signed-off-by: NAndy Fleming <afleming@gmail.com>
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由 Holger Freyther 提交于
The _config part is gone for sure, the _defconfig target could at least work. I have not verified this for all targets though.
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由 Stephen Warren 提交于
It's easier to Cc Masahiro on Kconfig-related changes with a git-mailrc alias. Signed-off-by: NStephen Warren <swarren@nvidia.com> Acked-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
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由 Masahiro Yamada 提交于
Reflect the latest build system to doc/README.SPL. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
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由 Masahiro Yamada 提交于
This document is too old and useless. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
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由 Heiko Schocher 提交于
if status register do never set MXC_CSPICTRL_TC, spi_xchg_single endless loops. Add a timeout here to prevent endless hang. Signed-off-by: NHeiko Schocher <hs@denx.de> Cc: Dirk Behme <dirk.behme@gmail.com> Reviewed-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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由 Simon Glass 提交于
This parameter should also be supported. Signed-off-by: NSimon Glass <sjg@chromium.org> Tested-by: NAjay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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由 Simon Glass 提交于
The SPI transaction delay is supposed to be measured from the end of one transaction to the start of the next. The code does not work that way, so fix it. Signed-off-by: NSimon Glass <sjg@chromium.org> Tested-by: NAjay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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由 Simon Glass 提交于
An incorrect message version is passed to the EC in some cases and the parameters of one function are switched. Fix these problems. Signed-off-by: NSimon Glass <sjg@chromium.org> Tested-by: NAjay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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由 Marek Vasut 提交于
It's usually a common pattern to free() the memory that we allocated. Implement this here to stop leaking memory. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Michal Simek <michal.simek@xilinx.com> Reviewed-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
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- 04 8月, 2014 3 次提交
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由 Simon Glass 提交于
Add support for re-relocation malloc() in arm's start-up code. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
At present arm defines CONFIG_SYS_GENERIC_GLOBAL_DATA, meaning that the global_data pointer is set up in board_init_f(). However it is actually set up before this, it just isn't zeroed. If we zero the global data before calling board_init_f() then we don't need to define CONFIG_SYS_GENERIC_GLOBAL_DATA. Make this change (on arm32 only) to simplify the init process. I don't have the ability to test aarch64 yet. Signed-off-by: NSimon Glass <sjg@chromium.org> Acked-by: NTom Rini <trini@ti.com>
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- 02 8月, 2014 17 次提交
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由 Boschung, Rainer 提交于
This patch configures the qrio to trigger a core reset on a CPU reset request. Signed-off-by: NRainer Boschung <rainer.boschung@keymile.com> Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Boschung, Rainer 提交于
To acheive this, the qrio_uprstreq() function that sets the UPRSTREQN flag in the qrio RESCNF reg is added. Signed-off-by: NRainer Boschung <rainer.boschung@keymile.com> Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Boschung, Rainer 提交于
Check the core timer status register (TSR) for watchdog reset, and and set the QRIO's reset reason flag REASON1[0] accordingly. This allows the appliction SW to identify the cpu watchdog as a reset reason, by setting the REASON1[0] flag in the QRIO. Signed-off-by: NRainer Boschung <rainer.boschung@keymile.com> Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Boschung, Rainer 提交于
To achieve this, the qrio_cpuwd_flag() function that sets the CPU watchdog flag in the REASON1 reg is added. Signed-off-by: NRainer Boschung <rainer.boschung@keymile.com> Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Boschung, Rainer 提交于
The booting of the board is now protected by the CPU watchdog. A failure during the boot phase will end up in board reset. Signed-off-by: NRainer Boschung <rainer.boschung@keymile.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Boschung, Rainer 提交于
When CONFIG_WATCHDOG is defined the board initialization just performs a WATCHDOG_RESET, an initialization of the watchdog is not done. This has been modified fot the MPC85xx, the board initialization calls its watchdog initialitzation allowing for full watchdog configuration very early in the boot phase. Signed-off-by: NRainer Boschung <rainer.boschung@keymile.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Boschung, Rainer 提交于
Function to inititialize the cpu watchdog added. Signed-off-by: NRainer Boschung <rainer.boschung@keymile.com> [York Sun: Add prototype in watchdog.h] Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Boschung, Rainer 提交于
For e500mc cores the watchdog timer period has to be set by means of a 6bit value, that defines the bit of the timebase counter used to signal a watchdog timer exception on its 0 to 1 transition. The macro used to set the watchdog period TCR_WP, was redefined for e500mc to support 6 WP setting. The parameter (x) given to the macro specifies the prescaling factor of the time base clock (fTB): watchdog_period = 1/fTB * 2^x Signed-off-by: NRainer Boschung <rainer.boschung@keymile.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Boschung, Rainer 提交于
TCR watchdog bit are overwritten when dec interrupt is enabled. This has been fixed with this patch. Signed-off-by: NRainer Boschung <rainer.boschung@keymile.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Dmitry Lifshitz 提交于
Add callback with __weak annotation to allow setup of environment partition number in runtime from a board file. Propagate mmc_switch_part() return value into init_mmc_for_env() instead of -1 in case of failure. Signed-off-by: NDmitry Lifshitz <lifshitz@compulab.co.il> Signed-off-by: NIgor Grinberg <grinberg@compulab.co.il> Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>
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由 Dmitry Lifshitz 提交于
Add missing mmc_get_env_addr() prototype in environment.h Signed-off-by: NDmitry Lifshitz <lifshitz@compulab.co.il> Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>
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由 Bo Shen 提交于
If the MCI IP version >= 0x300, it supports hight speed mode option, this patch enable it. Signed-off-by: NBo Shen <voice.shen@atmel.com> Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>
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由 Bo Shen 提交于
Add configuration register definition, this register only exists on MCI IP version >= 0x300. Signed-off-by: NBo Shen <voice.shen@atmel.com> Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>
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由 Bo Shen 提交于
The mode register is different between MCI IP version. So, according to MCI IP version to set the mode register. Signed-off-by: NBo Shen <voice.shen@atmel.com> Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>
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由 Chin Liang See 提交于
To fix the clock divider calculation error when the controller clock same as the operating frequency. This is known as bypass mode. In this mode, the divider should be 0. Signed-off-by: NChin Liang See <clsee@altera.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Mischa Jonker <mjonker@synopsys.com>
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由 Marek Vasut 提交于
Implement SD driver for the S3C24xx family. This implementation is currently only capable of using the PIO transfers, DMA is not supported. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Vladimir Zapolskiy <vz@mleia.com> Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>
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由 Marek Vasut 提交于
Unify the register structure so they can be easily used across all of S3C24xx lineup. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Vladimir Zapolskiy <vz@mleia.com> Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>
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- 01 8月, 2014 2 次提交
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由 Lubomir Rintel 提交于
Seems like the controller doesn't support the flag. None of the hi-speed cards I've tried could be read, while they successfully worked with the quirk enabled. Signed-off-by: NLubomir Rintel <lkundrak@v3.sk> Tested-by: NStephen Warren <swarren@wwwdotorg.org>
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由 DrEagle 提交于
This patch add Marvell kirkwood MVSDIO/MMC driver and enable it for Sheevaplugs and OpenRD boards. Signed-off-by: NGerald Kerma <drEagle@doukki.net> Reviewed-by: NStefan Roese <sr@denx.de> Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>
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- 31 7月, 2014 1 次提交
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由 Hans de Goede 提交于
The Banana Pi is an A20 based development board using Raspberry Pi compatible IO headers. It comes with 1 GB RAM, 1 Gb ethernet, 2x USB host, sata, hdmi and stereo audio out + various expansion headers: http://www.lemaker.org/Signed-off-by: NHans de Goede <hdegoede@redhat.com> Acked-by: NIan Campbell <ijc@hellion.org.uk>
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