- 22 4月, 2013 7 次提交
-
-
由 Stefan Roese 提交于
Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NScott Wood <scottwood@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
-
由 Stefan Roese 提交于
This will be used by the i.MX6 NAND support. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
-
由 Stefan Roese 提交于
This patch moves the following functions into the imx-common directory: - mxs_wait_mask_set() - mxs_wait_mask_clr() - mxs_reset_block() These are currently used by i.MX28. But the upcoming GPMI NAND port for i.MX6 will also use these functions. So lets move them to a common location to re-use them. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
-
由 Stefan Roese 提交于
The following headers are moved to a i.MX common location: - regs-common.h - regs-apbh.h - regs-bch.h - regs-gpmi.h - dma.h This way this header can be re-used also by other i.MX platforms. For example the i.MX6 which will need it for the upcoming NAND support. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
-
由 Fabio Estevam 提交于
mx6slevk board is a development board from Freescale based on the mx6 solo-lite processor. For details about mx6slevk, please refer to: http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=IMX6SLEVK&parentCode=i.MX6SL&fpsp=1Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
-
由 Fabio Estevam 提交于
mx6 solo-lite is another member of the mx6 series. For more information about mx6 solo-lite, please visit: http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX6SL&nodeId=018rH3ZrDRB24ASigned-off-by: NFabio Estevam <fabio.estevam@freescale.com>
-
由 Fabio Estevam 提交于
Instead of having the same PAD control definition in each MX6 variant pin file, place it into a common location. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
-
- 21 4月, 2013 1 次提交
-
-
由 Stefano Babic 提交于
-
- 17 4月, 2013 7 次提交
-
-
由 Shawn Guo 提交于
The ARM errata 742230 - "ARM errata: DMB operation may be faulty" is claimed for Cortex-A9 (r1p0..r2p2). Though i.MX6 uses a newer revision than r2p2, we are seeing a reboot failure on i.MX6 SMP build that can be fixed by applying the workaround for this errata. So for safety, let's define CONFIG_ARM_ERRATA_742230 to enable the workaround on i.MX6. Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
-
由 Simon Glass 提交于
Snow is missing a TMU node, and with TMU support this is not allowed, so it fails to boot. Add it. Signed-off-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
-
由 Simon Glass 提交于
The current code is causing errors like this on my toolchains: /usr/x86_64-pc-linux-gnu/armv7a-cros-linux-gnueabi/binutils-bin/2.22/ ld.bfd.real: failed to merge target specific data of file /usr/lib/gcc/ armv7a-cros-linux-gnueabi/4.7.x-google/libgcc.a(_divdi3.o) Use do_div() to avoid this. Signed-off-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
-
由 Vivek Gautam 提交于
Exynos5250 supports secondary USB device boot mode. If the iROM fails to download u-boot from the primary boot device (such as SD or eMMC), it will try to retrieve from the secondary boot device (such as USB). Signed-off-by: NNaveen Krishna Ch <ch.naveen@samsung.com> Signed-off-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NVivek Gautam <gautam.vivek@samsung.com> Acked-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
-
由 Stefan Roese 提交于
They never return anything also than 0, so lets change the function to void instead. Signed-off-by: NStefan Roese <sr@denx.de> Reviewed-by: NMarek Vasut <marex@denx.de>
-
由 Eric Benard 提交于
this is usefull when writing an UBI image which contains and UBIFS volume (check README.nand and UBI FAQ for more details) Signed-off-by: NEric Bénard <eric@eukrea.com> Acked-by: NOtavio Salvador <otavio@ossystems.com.br>
-
由 Philip Paeps 提交于
This makes mxc_iomux_set_input() work correctly. Previously, the incorrect offset of IOMUXSW_INPUT_CTL caused mxc_iomux_set_input() to write to the wrong register, possibly resulting in unexpected behaviour. Signed-off-by: NPhilip Paeps <philip@paeps.cx> Acked-by: NStefano Babic <sbabic@denx.de>
-
- 16 4月, 2013 13 次提交
-
-
由 Tom Warren 提交于
Beaver is a Tegra30 board that is nearly 100% compatible w/Cardhu. Add a Beaver build so it can begin to be differentiated, if need be. Signed-off-by: NTom Warren <twarren@nvidia.com> Reviewed-by: NStephen Warren <swarren@nvidia.com>
-
由 Tom Warren 提交于
As suggested by Stephen Warren, use tegra_get_chip() to return the pure CHIPID for a Tegra SoC (i.e. 0x20 for Tegra20, 0x30 for Tegra30, etc.) and rename tegra_get_chip_type() to reflect its true function, i.e. tegra_get_chip_sku(), which returns an ID like TEGRA_SOC_T25, TEGRA_SOC_T33, etc. Signed-off-by: NTom Warren <twarren@nvidia.com> Reviewed-by: NStephen Warren <swarren@nvidia.com>
-
由 Tom Warren 提交于
A comparison of registers between our internal NV U-Boot and u-boot-tegra/next showed some discrepancies in the MSELECT clock divisor programming. T20 doesn't have a MSELECT clk src reg. Signed-off-by: NTom Warren <twarren@nvidia.com> Reviewed-by: NStephen Warren <swarren@nvidia.com>
-
由 Tom Warren 提交于
T114 needs the SYSCTR0 counter initialized so the TSC can be read by the kernel. Do it in the bootloader since it's a write-once deal (secure/non-secure mode dependent). Signed-off-by: NTom Warren <twarren@nvidia.com> Reviewed-by: NStephen Warren <swarren@nvidia.com>
-
由 Tom Warren 提交于
Without this change, kernel fails at calling function cache_clean_flush during kernel early boot. Aprocryphally, intended for T114 only, so I check for a T114 SoC. Works (i.e. dalmore 3.8 kernel now starts printing to console). Signed-off-by: NTom Warren <twarren@nvidia.com>
-
由 Thierry Reding 提交于
Boot script support brings TEC in line with other Tegra boards. To enable booting a Linux kernel with initial ramdisk, also include support for the new FIT image type. Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de> Signed-off-by: NTom Warren <twarren@nvidia.com> Reviewed-by: NStephen Warren <swarren@nvidia.com>
-
由 Thierry Reding 提交于
Boot script support brings Plutux in line with other Tegra boards. In order to enable booting a Linux kernel with initial ramdisk, also add support for the new FIT image type. Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de> Signed-off-by: NTom Warren <twarren@nvidia.com> Reviewed-by: NStephen Warren <swarren@nvidia.com>
-
由 Thierry Reding 提交于
Boot script support brings Medcom-Wide in line with other Tegra boards. In order to enable booting a Linux kernel with initial ramdisk, also add support for the new FIT image type. Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de> Signed-off-by: NTom Warren <twarren@nvidia.com> Reviewed-by: NStephen Warren <swarren@nvidia.com>
-
由 Thierry Reding 提交于
Move the nand-controller node to the tegra20-tamonten.dtsi so that it can be shared between all derived boards. Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de> Signed-off-by: NTom Warren <twarren@nvidia.com> Reviewed-by: NStephen Warren <swarren@nvidia.com>
-
由 Tom Warren 提交于
A start vector fix was added by AneeshV for OMAP4 (commit 0d479b53), and caused the old monilithic Tegra builds to hang due to an undefined instruction trap. Previously, the code needed to run on both the AVP (ARM7TDI) and A9, and the AVP doesn't have a CP15 register. I corrected this in commit 6d6c0bae w/#ifndef CONFIG_TEGRA, but now that we use SPL, and boot the AVP w/o any ARMv7 code, I can revert my change, and make Aneesh's change apply to Tegra. Signed-off-by: NTom Warren <twarren@nvidia.com>
-
由 Tom Warren 提交于
Some 3rd-party flash tools use the -v (verify) option of crc32 command. Signed-off-by: NTom Warren <twarren@nvidia.com> Acked-by: NSimon Glass <sjg@chromium.org>
-
由 Stephen Warren 提交于
Make U-Boot aware of the T33 SKU of Tegra30, and treat it identically to any other Tegra30. An alternative would be to simply remove the SKU checking from tegra_get_chip_type(); most use of the value most likely simply wants to know the current chip, not the specific SKU. Or, the function could be split into separate tegra_get_chip() and tegra_get_sku() for the cases where differentiation really is required. I wonder whether tegra_get_chip_type() should printf() whenever any unkown chip/SKU is found, although perhaps the function is called so early that the printf() wouldn't actually make it to the UART anyway. Signed-off-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com> Acked-by: NSimon Glass <sjg@chromium.org>
-
由 Andre Przywara 提交于
The KVM and Xen hypervisors for the Cortex-A15 virtualization implementation need to be entered in HYP mode. Should the primary board firmware already enter HYP mode (Calxeda firmware does that), we should not deliberately drop back to SVC mode. Since U-boot does not use the MMU, running in HYP mode is just fine. Signed-off-by: NAndre Przywara <andre.przywara@linaro.org>
-
- 14 4月, 2013 10 次提交
-
-
由 Albert ARIBAUD 提交于
Signed-off-by: NAlbert ARIBAUD <albert.u.boot@aribaud.net>
-
由 Albert ARIBAUD 提交于
This target wants to check full SPL size, BSS included. Remove CONFIG_SPL_MAX_SIZE definition and instead define CONFIG_SPL_MAX_FOOTPRINT. Signed-off-by: NAlbert ARIBAUD <albert.u.boot@aribaud.net>
-
由 Albert ARIBAUD 提交于
This target wants to check full SPL size, BSS included. Remove CONFIG_SPL_MAX_SIZE definition and instead define CONFIG_SPL_MAX_FOOTPRINT. Signed-off-by: NAlbert ARIBAUD <albert.u.boot@aribaud.net>
-
由 Albert ARIBAUD 提交于
This target wants to check full SPL size, BSS included. Remove CONFIG_SPL_MAX_SIZE definition and instead define CONFIG_SPL_MAX_FOOTPRINT. Signed-off-by: NAlbert ARIBAUD <albert.u.boot@aribaud.net>
-
由 Albert ARIBAUD 提交于
Remove SPL-related ASSERT() in arch/arm/cpu/u-boot.lds as this file is never used for SPL builds. Rewrite the ASSERT() in arch/arm/cpu/u-boot-spl.lds to separately test image (text,data,rodata...) size, BSS size, and full footprint each against its own max, and make Tegra boards check full footprint. Also, output section mmutable is not used in SPL builds. Remove it. Finally, update README regarding the (now homogeneous) semantics of CONFIG_SPL_[BSS_]MAX_SIZE and add the new CONFIG_SPL_MAX_FOOTPRINT macro. Signed-off-by: NAlbert ARIBAUD <albert.u.boot@aribaud.net> Reported-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
-
由 Albert ARIBAUD 提交于
-
由 Andrew Gabbasov 提交于
Rework the waiting for transfer completion loop condition to continue waiting until both Transfer Complete and DMA End interrupts occur. Checking of DLA bit in Present State register looks not needed in addition to interrupts status checking, so it can be removed from the condition. Also, DMA Error condition is added to the list of data errors, checked in the loop. Signed-off-by: NAndrew Gabbasov <andrew_gabbasov@mentor.com>
-
由 Eric Nelson 提交于
The cache should invalidate the read buffer for the SD card interface after the transfer complete, not command-complete. Tested-by: NAndrew Gabbasov <Andrew_Gabbasov@mentor.com> Signed-off-by: NEric Nelson <eric.nelson@boundarydevices.com>
-
由 Albert ARIBAUD 提交于
-
由 Albert ARIBAUD 提交于
Commit 3ebd1cbc introduced compiler-generated __bss_start and __bss_end__ and commit c23561e7 rewrote all __bss_end__ as __bss_end. Their merge caused silent and harmless but potentially bug-inducing clashes between compiler- and linker- generated __bss_end symbols. Make __bss_end and __bss_start compiler-only, and create __bss_base and __bss_limit for linker-only use. Signed-off-by: NAlbert ARIBAUD <albert.u.boot@aribaud.net> Reported-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
-
- 13 4月, 2013 2 次提交
-
-
由 Fabio Estevam 提交于
The glitch in the SPI clock line, which commit 3cea335c (spi: mxc_spi: Fix spi clock glitch durant reset) solved, is back now and itwas re-introduced by commit d36b39bf (spi: mxc_spi: Fix ECSPI reset handling). Actually the glitch is happening due to always toggling between slave mode and master mode by configuring the CHANNEL_MODE bits in this reset function. Since the spi driver only supports master mode, set the mode for all channels always to master mode in order to have a stable, "glitch-free" SPI clock line. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
-
由 Otavio Salvador 提交于
Signed-off-by: NOtavio Salvador <otavio@ossystems.com.br> Acked-by: NFabio Estevam <fabio.estevam@freescale.com>
-