- 06 11月, 2018 3 次提交
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由 Stefan Roese 提交于
The new board version has the 2nd FPGA connected via CS# 0 instead of 2 on SPI bus 1. Change this setup in the DT accordingly. Please note that this change does still work on the old board version because the CS signal is not used on this board. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Add the "spi-flash" compatible string so that the generic sf_probe driver can probe the SPI flash on the theadorable Armada-XP board. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
With patch 49b23e03 (pci: mvebu: Increase size of PCIe default mapping) the mapping size for each PCI(e) controller was increased from 32MiB to 128MiB. This leads to problems on boards with multiple PCIe slots / ports which are unable to map all PCIe ports, e.g. the Armada-XP theadorable: DRAM: 2 GiB (667 MHz, 64-bit, ECC not enabled) SF: Detected m25p128 with page size 256 Bytes, erase size 256 KiB, total 16 MiB Cannot add window '4:f8', conflicts with another window PCIe unable to add mbus window for mem at f0000000+08000000 Model: Marvell Armada XP theadorable This patch moves the base address for the PCI(e) memory spaces from 0xe8000000 to the end of SDRAM (clipped to a max of 0xc0000000 right now). This gives move room and flexibility for PCI(e) mappings. Signed-off-by: NStefan Roese <sr@denx.de> Cc: VlaoMao <vlaomao@gmail.com> Tested-by: VlaoMao <vlaomao at gmail.com>
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- 04 11月, 2018 1 次提交
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- 03 11月, 2018 2 次提交
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git://git.denx.de/u-boot-mips由 Tom Rini 提交于
- replace the dynamic size of the relocation table with a fixed but configurable size - fixes non-working CONFIG_OF_SEPARATE=y due to invalid _end symbol
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由 Daniel Schwierzeck 提交于
Currently the size of the relocation table will be shrunk to the actual size needed. Although this gives a maximal space saving, it messes up the _end symbol. This breaks features like appended DTBs because the _end symbol doesn't point to the real end of the U-Boot binary. Remove the size shrinking and make the size of the relocation table fixed but configurable. This follows the Linux approach and the user can adjust the size to his needs. Also rename the relocation table section from .rel to .data.reloc to follow the Linux approach and to avoid ambiguities with the .rel.* sections added by the linker. Reported-by: NLars Povlsen <lars.povlsen@microsemi.com> Signed-off-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
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- 02 11月, 2018 15 次提交
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由 Marek Vasut 提交于
It is perfectly fine to write th DTCNTL TAP count and enable the SCC sampling clock operation in the same write. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
When the bus switches to 1.8V mode of operation, it is necessary to verify that the card correctly initiated and completed the voltage switch. This is done by reading out the state of DATA0 line. This patch implement support for reading out the state of the DATA0 line, so the MMC core code can correctly switch to 1.8V mode. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
Make sure to clear HS400 configuration when resetting the SCC block. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
Add check to avoid touching the SCC tuning registers in case the IP doesn't support them or if the support isn't in place yet. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
Preinitialize the SD card signals regulator to 3.3V, which is the default post-reset setting, to be sure the regulator is set to a valid value. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
Configure the clock settings before reconfiguring any other IO settings. This is required when the clock must be stopped before changing eg. the pin configuration or any of the other properties of the bus. Running the clock configuration first allows the MMC core to do just that. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
In case the controller performs card tuning, that is, sends MMC command 19 or 21, silence possible CRC error warning prints. The warnings are bound to happen, since the tuning will fail for some settings while searching for the optimal configuration of the bus and that is perfectly OK. This patch passes around the MMC command structure and adds check into tmio_sd_check_error() to avoid printing CRC error warning when the tuning happens. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
Properly handle return values and abort operations when they are non-zero. This is a minor improvement, which fixes two remaining unchecked return values. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
The SD UHS SDR12, SDR25, SDR50, SDR104, DDR50 and MMC HS200, HS400 modes all use 1.8V signaling, while all the legacy modes use 3.3V signaling. While there are extra modes which use 1.2V signaling, the existing hardware does not support those. Simplify the pinmux such that 3.3V signaling implies legacy mode pinmux and the rest implies UHS mode pinmux. This prevents the massive case statement from growing further. Moreover, it fixes an edge case where during SD 1.8V switch, the bus mode is still set to default while the signaling is already set to 1.8V, which results in an attempt to communicate with a 1.8V card using pins in 3.3V mode and thus communication failure. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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由 Marek Vasut 提交于
Patch "ARM: rmobile: Mark 4-64GiB as DRAM on Gen3" marked the entire 64bit DRAM space as cachable. On CortexA57, this might result in odd side effects, where the CPU tries to prefetch from those areas and if there is no DRAM backing them, CPU bus hang can happen. This patch fixes it by generating the mem_map structure based on the actual memory layout obtained from the DT, thus not marking areas without any DRAM behind them as cachable. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Fixes: c1ec3476 ("ARM: rmobile: Mark 4-64GiB as DRAM on Gen3") Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Add definition of the POCCTRL register and bits therein to R8A77990 E3 pincontrol driver. This allows the pincontrol driver to configure SDHI pin voltage according to power-source DT property. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Marek Vasut 提交于
Use fixed 4bit size for generating the DRV register element mask, not the size of the value, which can be smaller. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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git://git.denx.de/u-boot-arc由 Tom Rini 提交于
Just 2 non-functinal changes: 1. Rename of EMDK to EMSDP so it matches real marketing name 2. Add essential README for IoTDK
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由 Alexey Brodkin 提交于
Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>
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由 Alexey Brodkin 提交于
Real marketing name of the board was recently updated so to accommodate that change renaming the board and all related to it. Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>
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- 01 11月, 2018 10 次提交
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由 Sam Protsenko 提交于
This part should've been remove in commit 88d60db0 ("arm: ti: boot: Remove environment partition"), but I missed it somehow. Remove reading dtb file from environment partition on eMMC, as we don't have it anymore. Signed-off-by: NSam Protsenko <semen.protsenko@linaro.org>
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由 Jens Wiklander 提交于
Fixes possible resource leak in dm_test_tee() reported by Coverity. Reported-by: Coverity (CID: 184175) Signed-off-by: NJens Wiklander <jens.wiklander@linaro.org>
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由 Patrick Delaunay 提交于
This line is no more needed and can be removed. Only CONFIG_CMD_SOURCE is defined in Kconfig and used in defconfig files. CONFIG_SOURCE if not defined in source code and "config SOURCE" is not present in any Kconfig. Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
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由 Lokesh Vutla 提交于
The Makefile already tests for SPL_DM_REGULATOR_GPIO, but Kconfig does not provide it. This adds SPL_DM_REGULATOR_GPIO to Kconfig. Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Keerthy 提交于
Currently the base is 3 fix it 10 so that IDs follow decimal system. Signed-off-by: NKeerthy <j-keerthy@ti.com> Reviewed-by: NLokesh Vutla <lokeshvulta@ti.com>
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On our demo setup for SD card boot, the u-boot environment is in a FAT partition. This patch changes the default configuration, specifing that the u-boot environment is in a FAT partition instead of raw MMC. Signed-off-by: NAndrei Stefanescu <andrei.stefanescu@microchip.com> Acked-by: NEugen Hristev <eugen.hristev@microchip.com>
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The default bootcommand needs to be accurate w.r.t the nand memory map at http://www.at91.com/linux4sam/bin/view/Linux4SAM/AT91sam9x5ekMainPage#NAND_Flash_demo_Memory_map Updated to load kernel + dtb at right offsets and boot the zImage. Signed-off-by: NEugen Hristev <eugen.hristev@microchip.com>
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由 Martin Fuzzey 提交于
When the "w1 bus" command is used with no bus master present a data abort may occur. This is because uclass_first_device() returns zero, but sets the output struct udevice pointer to NULL in the no device found case. Fix w1_get_bus() to account for this and return an error code as is expected by the callers. Signed-off-by: NMartin Fuzzey <martin.fuzzey@flowbird.group> Reviewed-by: NEugen Hristev <eugen.hristev@microchip.com>
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由 Martin Fuzzey 提交于
Data abort was occurring when using "w1 bus" with a DS24B33 present. The abort occurred in the ds24xxx_probe() because the struct w1_device pointer was NULL. This is because that structure is allocated by the parent device uclass (by .per_child_platdata_auto_alloc_size) and thus the correct accessor is dev_get_parent_platdata() not dev_get_platdata() Signed-off-by: NMartin Fuzzey <martin.fuzzey@flowbird.group> Reviewed-by: NEugen Hristev <eugen.hristev@microchip.com>
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- 31 10月, 2018 4 次提交
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由 Simon Goldschmidt 提交于
Using imply for SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION instead of select ensures we can build without partition support (used to build a network boot only version of SPL and U-Boot). Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
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由 Stefan Roese 提交于
Commit 768f23dc ("ARM: socfpga: Put stack at the end of SRAM") broke those socfpga boards that keep the bootcounter at the end of the internal SRAM as the bootcounter needs 8 bytes by default and thus the very first SPL call to board_init_f_alloc_reserve overwrites the bootcounter. This patch allows to move the initial stack pointer down a bit by checking if CONFIG_SYS_BOOTCOUNT_ADDR is located in the internal SRAM area and then using this address as location for the start of the stack pointer. No new macros / defines are added by this approach. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
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由 Simon Goldschmidt 提交于
The 'status' variable in 'socfpga_load()' for both gen5 and arria10 is of type 'unsigned long' while it is always used as 'int' only. Change it to 'int'. Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
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git://git.denx.de/u-boot-mpc85xx由 Tom Rini 提交于
Workaround and bug fix for Freescale PowerPC Add workaround for Freescale USB erratum A005275. Correct RCW macros for T1080.
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- 30 10月, 2018 4 次提交
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由 Bin Meng 提交于
Per T1040RM (Rev. 1, 08/2015), there are 2 issues with the RCW EC2 settings. - The value of FSL_CORENET_RCWSR13_EC2_FM1_GPIO is wrong and should be 0x04000000 (value of 1 in RCW bit [420:421]) - Value of 2/3 are reserved in RCW bit [420:421], hence there is no macro FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NPoonam Aggrwal <poonam.aggrwal@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Bin Meng 提交于
Per T1040RM (Rev. 1, 08/2015), the value of FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT is wrong and should be 0x00000080 (bit 440 in the RCW). Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NPoonam Aggrwal <poonam.aggrwal@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Chris Packham 提交于
Workaround makes FS as default mode on all affected socs. Add support to check erratum-A005275 validity for an soc. This info is required to determine whether a given soc is affected by this erratum. Add quirk for this erratum "has_fsl_erratum_a005275" . This quirk is used to enable workaround for the errata Force FS mode as default by: - making EPS as FS - setting PFSC bit to disable HS chirping This workaround can be disabled by mentioning "no_erratum_a005275" in hwconfig string Signed-off-by: NChris Packham <judge.packham@gmail.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Tom Rini 提交于
Signed-off-by: NTom Rini <trini@konsulko.com>
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- 29 10月, 2018 1 次提交
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