This patch add support of hsdk platform-specific commands:

hsdk_clock set - set clock from axi_freq, cpu_freq and tun_freq
environment variables/command line arguments

hsdk_clock get - save clock frequencies to axi_freq, cpu_freq
and tun_freq environment variables

hsdk_clock print - show CPU, AXI, DDR and TUNNEL current
clock frequencies.

hsdk_clock print_all - show all currently used clock frequencies.

hsdk_init - setup board HW in one of pre-defined configuration
(hsdk_hs34 / hsdk_hs36 / hsdk_hs36_ccm / hsdk_hs38 /
hsdk_hs38_ccm / hsdk_hs38x2 / hsdk_hs38x3 / hsdk_hs38x4)

hsdk_go - run baremetal application on hsdk configured
by hsdk_init command.

This patch changes default behaviour of 'bootm' command:
now we are able to set number of CPUs to be kicked by setting
'core_mask' environment variable before 'bootm' command run.
Signed-off-by: NEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>

Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>

Some device tree nodes (like ethernet, ohci, ehci) in axs10x_mb.dtsi
were copied from linux device tree, so they have interrupts properties.
As we don't use interrupts in uboot we don't have interrupt controller
node in AXS10x device tree. In result we get warnings when we compile
such device tree.

So remove unused interrupts properties to get rid of this warnings.
Signed-off-by: NEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>

Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: NKen Ma <make@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

This patch enabled PCIe port on both devel-board
and espressobin board.

Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: NWilson Ding <dingwei@marvell.com>
Signed-off-by: NKen Ma <make@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NWilson Ding <dingwei@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: NKen Ma <make@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

This patch introduced the Aardvark PCIe driver based
driver model.
The PCIe driver is supposed to work in Root Complex
mode. It only supports X1 lane width.
Signed-off-by: NWilson Ding <dingwei@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/38725Reviewed-by: NVictor Gu <xigu@marvell.com>
Reviewed-by: NHua Jing <jinghua@marvell.com>
Tested-by: NHua Jing <jinghua@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: NKen Ma <make@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

This patch added a new region of 32MiB AT 0xe800.0000
to Armada37x0's memory map. This region is supposed to
be mapped in MMU in order to enable the access to the
PCI I/O or MEM resources.
Signed-off-by: NWilson Ding <dingwei@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/38724Tested-by: NiSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: NVictor Gu <xigu@marvell.com>
Signed-off-by: NKen Ma <make@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: NStefan Roese <sr@denx.de>

Since the new pinctrl/gpio driver is used, so this patch removes
the old board specific pin control settings.

Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: NKen Ma <make@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

The commit "arm64: mvebu: Add pinctrl nodes for Armada 3700" has
added new pinctrl nodes.
This reverts commit f7cab0f9.

Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: NKen Ma <make@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Reviewed-on: http://vgitil04.il.marvell.com:8080/43289Tested-by: NiSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: NKostya Porotchkin <kostap@marvell.com>
Reviewed-by: NIgal Liberman <igall@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: NKen Ma <make@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

This patch corrects below mpp definitions for armada 3720 DB board
and ESPRESSOBin board:
- "smi" pins group is added and "smi" function is set for eth0;
- Now pcie pins are used as gpio to implement PCIe function in
  hardware, so "pcie" group function is changed to "gpio".

Reviewed-on: http://vgitil04.il.marvell.com:8080/43287Reviewed-by: NHua Jing <jinghua@marvell.com>
Tested-by: NiSoC Platform CI <ykjenk@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: NKen Ma <make@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

This patch corrects below mpp definitions:
 - The sdio_sb group is composed of 6 pins and not 5;
 - The rgmii group contains pins mpp2[17:6] and not mpp2[19:6];
 - Pin of group "pmic0" is mpp1[6] but not mpp1[16];
 - Pin of group "pmic1" is mpp1[7] but not mpp1[17];
 - A new group "smi" is added in A0 with 2 pins - mpp2[19:18], its
   bitmask is bit4;
 - Group "pcie1" has 3 pins in A0 - mpp2[5:3], its bit mask is
   bit5 | bit9 | bit10 but not bit4;
 - Group "ptp" has 3 pins in A0 as Z1, but its bitmask is changed to
   bit11 | bit12 | bit13.

Reviewed-on: http://vgitil04.il.marvell.com:8080/43288Tested-by: NiSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: NHua Jing <jinghua@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: NKen Ma <make@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

For armada_37xx_update_reg(), the parameter offset should be pointer so
that it can be updated, otherwise offset will keep old value, and then
when offset is larger than or equal to 32 the mask calculated by
"BIT(offset)" will be 0 in gpio chip hook functions, it's an error,
this patch set offset parameter of armada_37xx_update_reg() as pointer.

Reviewed-on: http://vgitil04.il.marvell.com:8080/43287Reviewed-by: NHua Jing <jinghua@marvell.com>
Tested-by: NiSoC Platform CI <ykjenk@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: NKen Ma <make@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Pin 23 on South bridge does not belong to the rgmii group. It belongs to
a separate group which can have 3 functions.

Due to this the fix also have to update the way the functions are
managed. Until now each groups used NB_FUNCS(which was 2) functions. For
the mpp23, 3 functions are available but it is the only group which needs
it, so on the loop involving NB_FUNCS an extra test was added to handle
only the functions added.

The bug was visible when the gpio regulator used the gpio 23, the whole
rgmii group was setup to gpio which broke the Ethernet support on the
Armada 3720 DB board. Thanks to this patch, the UHS SD cards (which need
the vqmmc) _and_ the Ethernet work again.

Reviewed-on: http://vgitil04.il.marvell.com:8080/43284Reviewed-by: NHua Jing <jinghua@marvell.com>
Tested-by: NiSoC Platform CI <ykjenk@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: NKen Ma <make@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

The number of pins in South Bridge is 30 and not 29. There is a fix for
the driver for the pinctrl, but a fix is also need at device tree level
for the GPIO.

Reviewed-on: http://vgitil04.il.marvell.com:8080/43286Reviewed-by: NHua Jing <jinghua@marvell.com>
Tested-by: NiSoC Platform CI <ykjenk@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: NKen Ma <make@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

On the south bridge we have pin from 0 to 29, so it gives 30 pins (and
not 29).

Reviewed-on: http://vgitil04.il.marvell.com:8080/43285Tested-by: NiSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: NHua Jing <jinghua@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: NKen Ma <make@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Add mmc pins, pcie pins and sdio pins definition and do these pins'
configuration for DB board and espressobin board;
Add uart2 pins configuration for DB board.

Reviewed-on: http://vgitil04.il.marvell.com:8080/40914Reviewed-by: NWilson Ding <dingwei@marvell.com>
Tested-by: NWilson Ding <dingwei@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: NKen Ma <make@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Reviewed-on: http://vgitil04.il.marvell.com:8080/40913Reviewed-by: NWilson Ding <dingwei@marvell.com>
Tested-by: NWilson Ding <dingwei@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: NKen Ma <make@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

This patch enable the PINCTRL and GPIO support, including the GPIO
command on the Armada 3720 espressobin board.

Reviewed-on: http://vgitil04.il.marvell.com:8080/40746Tested-by: NiSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: NWilson Ding <dingwei@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: NKen Ma <make@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: NKen Ma <make@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

The various load address values are taken from the a37xx configuration
and match the dowstream 'u-boot-2017.03-armada-17.10' release where
appropriate.
Signed-off-by: NMark Kettenis <kettenis@openbsd.org>
Signed-off-by: NStefan Roese <sr@denx.de>

The kwbimage format is reading beyond its header structure if it
misdetects a Xilinx Zynq image and tries to read it. Fix it by
sanity checking that the header we want to read fits inside our
file size.
Signed-off-by: NAlexander Graf <agraf@suse.de>
Tested-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NStefan Roese <sr@denx.de>
Signed-off-by: NStefan Roese <sr@denx.de>

This makes the network devices usable when booting a blank board over
UART, with no pre-configured MAC address stored in the environment area.
Signed-off-by: NBaruch Siach <baruch@tkos.co.il>
Reviewed-by: NStefan Roese <sr@denx.de>
Signed-off-by: NStefan Roese <sr@denx.de>

Currently, ATU (address translation unit) implementation doesn't
support translate addresses > 32 bits.

This patch allows to configure ATU correctly for different
memory accesses (memory, configuration and IO).
The same approach is used in Linux Kernel.
Signed-off-by: NIgal Liberman <igall@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

On x86 platforms, U-Boot does not pass Device Tree data to the kernel.
This prevents the kernel from using FDT loaded by U-Boot.

Read the working FDT address from the "fdtaddr" environment variable
and add a copy of the FDT data to the kernel setup_data list.
Signed-off-by: NIvan Gorinov <ivan.gorinov@intel.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
[bmeng: add #include <linux/libfdt.h> to zimage.c to fix build error]
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>

Use dm_pci_map_bar function for BAR mapping. This has the advantage
of clearing BAR flags and and only accepting mapped memory.
Signed-off-by: NBernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Reviewed-by: NHannes Schmelzer <hannes.schmelzer@br-automation.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

It makes no sense to set a PCI region that has 0 size.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

PCI enumeration may happen very early on an x86 board. The board
information pointer should have been checked in decode_regions()
as its space may not be allocated yet.

With this commit, Intel Galileo board boots again.

Fixes: 664758c3 ("pci: Fix decode regions for memory banks")
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

The get_codeseg32() wants to know if a passed in descriptor has
flag GDT_NOTSYS set (desc & GDT_NOTSYS), not whether desc and
GDT_NOTSYS are not != 0 (desk && GDT_NOTSYS).

This is an obvious typo. Fix it up.
Signed-off-by: NAlexander Graf <agraf@suse.de>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Enable CONFIG_OF_BOAD to support delivery dtb to u-boot
at run time instead of embedded.

There are two methods to delivery dtb.
 1 Pass from loader:
   When u-boot boot from RAM, gdb or loader can pass dtb
   via a2 to u-boot dynamically. Of course gdb or loader
   shall be in charge of dtb delivery.

 2 Configure CONFIG_SYS_FDT_BASE:
   It can be configured as RAM or ROM base statically,
   no mater u-boot boot from RAM or ROM.
   If it was configured as ROM base, dtb can be burned
   into ROM(spi flash) by spi driver.

Meanwhile remove CONFIG_SKIP_LOWLEVEL_INIT which is
useless in nx25-ae250 configuration.
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>

Remove CONFIG_MMC_NDS32 from the three config
(adp-ae3xx_defconfig, adp-ag101p_defconfig, nx25-ae250_defconfig).
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>

nsd32_mmc was created to support ftsdc010 dm.
It is not necessary to separate both, so merge it
to ftsdc010.
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>

Convert CONFIG_FTSDC010_SDIO to Kconfig.
So CONFIG_FTSDC010_SDIO can also be
removed from config_whitelist.txt.
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>

CONFIG_FTSDC010_NUMBER was not used anymore,
can be removed now.

So CONFIG_FTSDC010_NUMBER
can also be removed from config_whitelist.txt.
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>

After drop non-dm code of ftsdc010, the sd register
base definition can be droppped now.

So CONFIG_FTSDC010_BASE and CONFIG_FTSDC010_BASE_LIST both
can be removed from config_whitelist.txt
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>

Remove board_mmc_init() in adp-ag101p, adp-ae3xx
and nx25-ae250 boards.
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>