- 17 2月, 2009 17 次提交
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由 Wolfgang Grandegger 提交于
The TQM8548_BE is a variant of the TQM8548 module with NAND and CAN interface. With NAND support, the image is significantly larger and TEXT_BASE is adjusted accordingly. U-Boot can be built for this module with "$ make TQM8548_BE_config". Signed-off-by: NWolfgang Grandegger <wg@grandegger.com>
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由 Wolfgang Grandegger 提交于
The TQM8548_AG module does not have the standard PCI/PCI-X interface connected but just the PCI Express interface . So far it was not possible to disable it without disabling the complete PCI interface (CONFIG_PCI) including PCI Express. Signed-off-by: NWolfgang Grandegger <wg@grandegger.com>
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由 Wolfgang Grandegger 提交于
As the reset vector is located at 0xfffffffc, all flash sectors from the beginning of the U-Boot binary to 0xffffffff must be protected. On the TQM8548-AG having small sectors at the end of the flash it happened that the last two sector were not protected and an "erase all" left an un-bootable system behind: Bank # 2: CFI conformant FLASH (32 x 16) Size: 32 MB in 270 Sectors AMD Standard command set, Manufacturer ID: 0xEC, Device ID: 0x257E Erase timeout: 8192 ms, write timeout: 1 ms FFFA0000 E RO FFFC0000 RO FFFE0000 RO FFFE4000 RO FFFE8000 RO FFFEC000 RO FFFF0000 RO FFFF4000 RO FFFF8000 E FFFFC000 The same bug seems to be in drivers/mtd/cfi_flash.c:flash_init() and many board BSPs as well. Signed-off-by: NWolfgang Grandegger <wg@grandegger.com>
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由 Peter Tyser 提交于
- Update style of 86xx CPU information on boot to more closely match 85xx boards - Fix detection of 8641/8641D - Use strmhz() to display frequencies - Display L1 information - Display L2 cache size - Fixed CPU/SVR version output == Before == Freescale PowerPC CPU: Core: E600 Core 0, Version: 0.2, (0x80040202) System: Unknown, Version: 2.1, (0x80900121) Clocks: CPU:1066 MHz, MPX: 533 MHz, DDR: 266 MHz, LBC: 133 MHz L2: Enabled Board: X-ES XPedite5170 3U VPX SBC == After == CPU: 8641D, Version: 2.1, (0x80900121) Core: E600 Core 0, Version: 2.2, (0x80040202) Clock Configuration: CPU:1066.667 MHz, MPX:533.333 MHz DDR:266.667 MHz (533.333 MT/s data rate), LBC:133.333 MHz L1: D-cache 32 KB enabled I-cache 32 KB enabled L2: 512 KB enabled Board: X-ES XPedite5170 3U VPX SBC Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
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由 Peter Tyser 提交于
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
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由 Peter Tyser 提交于
Update the 86xx reset sequence to try executing a board-specific reset function. If the board-specific reset is not implemented or does not succeed, then assert #HRESET_REQ. Using #HRESET_REQ is a more standard reset procedure than the previous method and allows all board peripherals to be reset if needed. Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
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由 Kumar Gala 提交于
Previously if we >=4G of memory and !CONFIG_PHYS_64BIT we'd report an error and hang. Instead of doing that since DDR is mapped in the lowest priority LAWs we setup the DDR controller and the max amount of memory we report back is what we can map (CONFIG_MAX_MEM_MAPPED) Signed-off-by: NKumar Gala <galak@kernel.crashing.org> Acked-by: NBecky Bruce <beckyb@kernel.crashing.org>
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由 Srikanth Srinivasan 提交于
Added various p2020 processor specific details: * SVR for p2020, p2020E * immap updates for LAWs and DDR on p2020 * LAW defines related to p2020 Signed-off-by: NSrikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: NTravis Wheatley <Travis.Wheatley@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
Added some info that is printed out when we boot to distiquish if we built MPC8572DS_config vs MPC8572DS_36BIT_config since they have different address maps. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Andy Fleming 提交于
The device tree's PHY addresses need to be fixed up if we're using the SGMII Riser Card. The 8572, 8536, and 8544 DS boards were modified to call this function. Code idea taken from Liu Yu <yu.liu@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Andy Fleming 提交于
Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Andy Fleming 提交于
This allows code to iterate through the ethernet devices Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Kumar Gala 提交于
In the 36-bit physical config for MPC8572DS when need the start address of memory and it size to be kept in phys_*_t instead of a ulong since we support >4G of memory in the config and ulong cant represent that. Otherwise we end up seeing the memory node in the device tree reporting back we have memory starting @ 0 and of size 0. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
When we introduced the 36-bit config of the MPC8572DS board we had the wrong PCI MEM bus address map. Additionally, the change to the address map exposes a small issue in our dummy read on the ULI bus. We need to use the new mapping functions to handle that read properly in the 36-bit config. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
Previously we only allowed power-of-two memory sizes and didnt handle >2G of memory. Now we will map up to CONFIG_MAX_MEM_MAPPED and should properly handle any size that we can make in the TLBs we have available to us Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
If we only have one controller we can completely ignore how memctl_intlv_ctl is set. Otherwise other levels of code get confused and think we have twice as much memory. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
Only print 4 cpu freq per line. This way when we have 8 cores its a bit more readable. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 16 2月, 2009 4 次提交
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由 Abraham, Thomas 提交于
The LUN number is not part of the Command Descriptor Block (CDB) for scsi inquiry, request sense, test unit ready, read capacity and read10 commands. This patch removes the LUN number information from the CDB. Signed-off-by: NThomas Abraham <t-abraham@ti.com> Signed-off-by: NRemy Bohmer <linux@bohmer.net>
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由 Atin Malaviya 提交于
V3: Fixed line-wrap problem due to user error in mail! Added usb_configured() checks in usbtty_puts() and usbtty_putc() to get around a hang when usb is not connected and the user has set up multi-io (setenv stdout serial,usbtty etc). Got rid of redundant __attribute__((packed)) directives that were causing warnings from gcc. Signed-off-by: NAtin Malaviya <atin.malaviya@gmail.com> Signed-off-by: NRemy Bohmer <linux@bohmer.net>
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- 14 2月, 2009 1 次提交
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由 Guennadi Liakhovetski 提交于
i.MX31 powers on with most clocks running, so, after a power on this explicit clock start up is not required. However, as Linux boots it disables most clocks to save power. This includes the I2C clock. If we then soft reboot from Linux the I2C clock stays off. This breaks the phycore, which has its environment in I2C EEPROM. Fix the problem by explicitly starting the clock in I2C driver initialisation routine. Signed-off-by: NGuennadi Liakhovetski <lg@denx.de> Ack-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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- 12 2月, 2009 17 次提交
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由 Mike Frysinger 提交于
The Blackfin i2c driver has been rewritten thus the special ifdefs in the common code are no longer needed. Signed-off-by: NMike Frysinger <vapier@gentoo.org>
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由 Heiko Schocher 提交于
With actual u-boot compiling the mgcoge port fails, because since commit ba705b5b it is necessary to define CONFIG_NET_MULTI. Seems to me the mgcoge port is the only actual existing 8260 port who uses CONFIG_ETHER_ON_SCC, so no other 8260 port needed to be fixed. Signed-off-by: NHeiko Schocher <hs@denx.de>
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由 Dirk Eibach 提交于
Signed-off-by: NDirk Eibach <eibach@gdsys.de> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Carolyn Smith 提交于
This fixes the initialization of the SDRAM_CODT register in the ppc4xx DDR2 initialization code. It also removes use of the SDRAM_CODT_FEEDBACK_RCV_SINGLE_END and SDRAM_CODT_FEEDBACK_DRV_SINGLE_END #define's since they are reserved bits. Signed-off-by: NCarolyn Smith <carolyn.smith@tektronix.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Some AMCC eval boards do have a board_eth_init() function calling pci_eth_init(). These boards need to call cpu_eth_init() explicitly now with the new eth_init rework. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Adam Graham 提交于
The criteria of the AMCC SDRAM Controller DDR autocalibration U-Boot code is to pick the largest passing write/read/compare window that also has the smallest SDRAM_RDCC.[RDSS] Read Sample Cycle Select value. On some Kilauea boards the DDR autocalibration algorithm can find a large passing write/read/compare window with a small SDRAM_RDCC.[RDSS] aggressive value of Read Sample Cycle Select value "T1 Sample". This SDRAM_RDCC.[RDSS] Read Sample Cycle Select value of "T1 Sample" proves to be to aggressive when later on U-Boot relocates into DDR memory and executes. The memory traces on the Kilauea board are short so on some Kilauea boards the SDRAM_RDCC.[RDSS] Read Sample Cycle Select value of "T1 Sample" shows up as a potentially valid value for the DDR autocalibratiion algorithm. The fix is to define a weak default function which provides the minimum SDRAM_RDCC.[RDSS] Read Sample Cycle Select value to accept for DDR autocalibration. The default will be the "T2 Sample" value. A board developer who has a well defined board and chooses to be more aggressive can always provide their own board specific string function with the more aggressive "T1 Sample" value or stick with the default minimum SDRAM_RDCC.[RDSS] value of "T2". Also put in a autocalibration loop fix for case where current write/read/compare passing window size is the same as a prior window size, then in this case choose the write/read/compare result that has the associated smallest RDCC T-Sample value. Signed-off-by: NAdam Graham <agraham@amcc.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
CONFIG_SDRAM_PPC4xx_IBM_DDR2 is not set when include/asm-ppc/config.h is included. So for katmai, CONFIG_MAX_MEM_MAPPED will get set to 256MB. It makes perfect sense to set CONFIG_MAX_MEM_MAPPED to 2GB for all PPC4xx boards right now. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Wolfgang Denk 提交于
Signed-off-by: NWolfgang Denk <wd@denx.de>
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由 Peter Tyser 提交于
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
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由 Heiko Schocher 提交于
Signed-off-by: NHeiko Schocher <hs@denx.de>
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由 Heiko Schocher 提交于
This patch adds the configuration option CONFIG_SYS_SMC_RXBUFLEN. With this option it is possible to allow the receive buffer for the SMC on 8xx to be greater then 1. In case CONFIG_SYS_SMC_RXBUFLEN == 1 this driver works as the old version. When defining CONFIG_SYS_SMC_RXBUFLEN also CONFIG_SYS_MAXIDLE must be defined to setup the maximum idle timeout for the SMC. Signed-off-by: NHeiko Schocher <hs@denx.de>
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由 Mike Frysinger 提交于
Move global '#ifdef CONFIG_xxx .... #endif' out of the .c files and into the COBJS-$(CONFIG_xxx) in the Makefile. Also delete unused var in kgdb code in the process. Signed-off-by: NMike Frysinger <vapier@gentoo.org>
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由 Mike Frysinger 提交于
Signed-off-by: NMike Frysinger <vapier@gentoo.org>
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由 Jerry Van Baren 提交于
At some point an intentional double space at the end of the sentence got changed into a tab in the GPL header line: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the This patch fixes the damage. Signed-off-by: NGerald Van Baren <vanbaren@cideas.com>
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由 Heiko Schocher 提交于
If on your board is more than one flash, you must know the size of every single flash, for example, for updating the DTS before booting Linux. So make this function flash_get_info() extern, and you can have all info about your flashes. Signed-off-by: NHeiko Schocher <hs@denx.de> Signed-off-by: NStefan Roese <sr@denx.de>
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- 10 2月, 2009 1 次提交
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由 Ben Warren 提交于
Added new CONFIG options for the three type of MAC-PHY interconnect and applied them all relevant board config files Signed-off-by: NBen Warren <biggerbadderben@gmail.com>
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