- 23 4月, 2015 2 次提交
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由 Prabhakar Kushwaha 提交于
Increase malloc length for more than 2M. Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Prabhakar Kushwaha 提交于
LDPAA Ethernet driver is a freescale's new ethernet driver based on Layerscape architecture. Every ethernet driver controls on DPNI object. Where all DPNIs share one common DPBP and DPIO object to support Rx and Tx flows. Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> CC: Cristian Sovaiala <cristian.sovaiala@freescale.com> CC: Bogdan Hamciuc <bogdan.hamciuc@freescale.com> CC: J. German Rivera <German.Rivera@freescale.com> [York Sun: s/NetReceive/net_process_received_packet] Reviewed-by: NYork Sun <yorksun@freescale.com>
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- 22 4月, 2015 14 次提交
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由 Prabhakar Kushwaha 提交于
Freescale's Layerscape Management Complex (MC) provide support various objects like DPRC, DPNI, DPBP and DPIO. Where: DPRC: Place holdes for other MC objectes like DPNI, DPBP, DPIO DPBP: Management of buffer pool DPIO: Used for used to QBMan portal DPNI: Represents standard network interface These objects are used for DPAA ethernet drivers. Signed-off-by: NJ. German Rivera <German.Rivera@freescale.com> Signed-off-by: NLijun Pan <Lijun.Pan@freescale.com> Signed-off-by: NStuart Yoder <stuart.yoder@freescale.com> Signed-off-by: NGeoff Thorpe <Geoff.Thorpe@freescale.com> Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com> Signed-off-by: NCristian Sovaiala <cristian.sovaiala@freescale.com> Signed-off-by: Npankaj chauhan <pankaj.chauhan@freescale.com> Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Bhupesh Sharma 提交于
This patch adds description for NOR flash layout (firmware images) in the README file for LS2085A platforms. Signed-off-by: NBhupesh Sharma <bhupesh.sharma@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Bhupesh Sharma 提交于
The Debug Server driver is responsible for loading the Debug server FW on the Service Processor (Cortex-A5 core) on LS2085A like SoCs and then polling for the successful initialization of the same. TOP MEM HIDE is adjusted to ensure the space required by Debug Server FW is accounted for. MC uses the DDR area which is calculated as: MC DDR region start = Top of DDR - area reserved by Debug Server FW Signed-off-by: NBhupesh Sharma <bhupesh.sharma@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Zhao Qiang 提交于
Muram will power off during deepsleep, and the microcode of qe in muram will be lost, it should be reload when resume. Signed-off-by: NZhao Qiang <B45475@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Zhao Qiang 提交于
Muram will power off during deepsleep, and the microcode of qe in muram will be lost, it should be reload when resume. Signed-off-by: NZhao Qiang <B45475@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Nikhil Badola 提交于
Check if USB Erratum A005697 is applicable on BSC913x and add corresponding property in the device tree via device tree fixup which is used by linux driver Signed-off-by: NNikhil Badola <nikhil.badola@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Minghuan Lian 提交于
1. LS2085a provides PCIE_LUT_DBG register rather than PCIE_LDBG to show the link status, so the patch fixes it. 2. Increase the delay time to make sure that link training has finished. 3. Return invalid value when accessing multi-function device 4. For LS2085a DBI_RO_WR_EN bit is cleared as default, so we must set this bit before change DBI register value. Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com> Signed-off-by: NMinghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Minghuan Lian 提交于
The patch uses the common function name ft_pci_setup to replace ft_pcie_setup, then removes unnecessary pcie_layerscape.h because all the functions have been declared in common.h. Signed-off-by: NMinghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Nikhil Badola 提交于
Add following affected SOCs and their personalities for USB Erratum A007792 : T1040 Rev 1.1 T1024 Rev 1.0 Signed-off-by: NNikhil Badola <nikhil.badola@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Nikhil Badola 提交于
Identify soc(s) having dual phy so as to add "utmi_dual" as phy_mode for all these socs. This is required for supporting deel-sleep feature in linux for usb driver Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: NNikhil Badola <nikhil.badola@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 gaurav rana 提交于
1. Default environment will be used for secure boot flow which can't be edited or saved. 2. Command for secure boot is predefined in the default environment which will run on autoboot (and autoboot is the only option allowed in case of secure boot) and it looks like this: #define CONFIG_SECBOOT \ "setenv bs_hdraddr 0xe8e00000;" \ "esbc_validate $bs_hdraddr;" \ "source $img_addr;" \ "esbc_halt;" #endif 3. Boot Script can contain esbc_validate commands and bootm command. Uboot source command used in default secure boot command will run the bootscript. 4. Command esbc_halt added to ensure either bootm executes after validation of images or core should just spin. Signed-off-by: NRuchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: NGaurav Rana <gaurav.rana@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Alison Wang 提交于
On QDS board with DDR4 DIMM, LPUART is used as console output to verify DCU driver. This patch adds ls1021aqds_ddr4_nor_lpuart_defconfig for this support. Signed-off-by: NAlison Wang <alison.wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Yao Yuan 提交于
Freescale LS1021ATWR share some pins. Hwconfig option is used to allows users to choose the pin functions. Signed-off-by: NYuan Yao <yao.yuan@freescale.com> [York Sun: revised commit message] Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Alison Wang 提交于
For LS102xA, some workarounds are only used in VER1.0, so silicon version detection are added for QDS and TWR boards. Signed-off-by: NAlison Wang <alison.wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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- 21 4月, 2015 22 次提交
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由 Linus Walleij 提交于
commit aed2fbef "dm: serial: Tidy up the pl01x driver" caused a regression on (real hardware) PL010 by omitting to update the line control register when switching baudrate. Fix this by inlining the missing write to the baud control register. Also renaming the set_line_control() function to pl011_set_line_control() since this function is clearly PL011-specific, and it won't suffice to call that to set up line control. Tested on the Integrator/AP hardware. Cc: Simon Glass <sjg@chromium.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Andrey Skvortsov 提交于
two CMD_DNS options were added by commit 60296a83 ("commands: add more command entries in Kconfig") Signed-off-by: NAndrey Skvortsov <andrej.skvortzov@gmail.com> Acked-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Bin Meng 提交于
The name "pch_gbe.%x" exceeds the limit of the name in the 'struct eth_device'. Rename it as just "pch_gbe". Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
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由 Michal Simek 提交于
Use phys_addr_t which is used in function prototype in system.h. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Shengzhou Liu 提交于
commit 3c6928fd "net: phy: fix warnings with W=1" caused some PHYs(e.g. CS4315/CS4340) not working. This patch fixes the warning and make those special PHYs working as well. Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
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由 Luca Ellero 提交于
This patch adds a support for KSZ8081MNX in MII mode. Signed-off-by: NLuca Ellero <luca.ellero@brickedbrain.com> Acked-by: NPavel Machek <pavel@denx.de>
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由 Tim James 提交于
When accessing PHY registers it is often desirable to only update selected bits, so it is necessary to first read the current value before writing back an modified value with the relevant bits updated. To simplify this and to allow such operations to be incorporated into simple shell scripts propose adding a 'modify' option to the existing mii command, which takes a mask indicating the bits to be updated in addition to a data value containing the new bits, ie, <updated> = (<data> & <mask>) | (<current> & ~<mask>). Signed-off-by: NTim <tim.james@macltd.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Joe Hershberger <joe.hershberger@gmail.com> Cc: Jeroen Hofstee <jeroen@myspectrum.nl> Cc: Tom Rini <trini@konsulko.com> Cc: Tim <tim.james@macltd.com>
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由 Joe Hershberger 提交于
Update to my corporate email and make the supported filter and aliases more accurate. Signed-off-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Thierry Reding 提交于
Turn ioaddr into an unsigned long rather than a sized 32-bit variable. While at it, fix a couple of pointer to integer cast size mismatch warnings by casting through unsigned long going from pointers to integers and vice versa. Cc: Joe Hershberger <joe.hershberger@gmail.com> Signed-off-by: NThierry Reding <treding@nvidia.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Codrin Ciubotariu 提交于
Some Realtek Ethernet PHYs, like RTL8211D(G/N) and RTL8211E(G), have interrupts enabled by default. If the interrupt is not treated later by the OS and the PHY's interrupt line is enabled and shared with other interrupts, the system will get an interrupt storm. This patch disables the interrupt for PHY devices that use one of the current Realtek Ethernet PHY drivers. Some of Realtek Ethernet PHYs, such as RTL8211B(L) have the interrupt masked. In this case, the functionality of the PHY should not be afected since this patch brings INER and INSR registers to their default values. Signed-off-by: NCodrin Ciubotariu <codrin.ciubotariu@freescale.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Scott Wood 提交于
U-Boot on this board grew a long time ago past the 384 KiB that it reserves for the U-Boot image, before the environment. Thus, saveenv overwrites the U-Boot image and bricks the board. I tried to find out when U-Boot grew beyond this point, but there is a long stretch in the history where this board did not build -- and AFAICT when it did fit in 384 KiB, it was missing vital features such as fdt support. Turning off CONFIG_VIDEO was not enough to make it fit. Thus, I don't think we have any choice other than to move the environment. Signed-off-by: NScott Wood <scottwood@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Shengzhou Liu 提交于
CONFIG_PHY_AQ1202 is no longer needed, use CONFIG_PHY_AQUANTIA. Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Scott Wood 提交于
U-Boot does not have system calls (the services it exposes to standalone commands use a different mechanism), so the syscall handler is dead code. It's also broken code, as it assumes it is located at 0xc00 -- while even before the patch to stop relocating exception vectors to 0, U-Boot had the syscall at 0x900. The critical and machine check return paths are never called -- the regular exception return path is used instead, which works because xSRR0/1 have already been saved and can be restored via the regular SRR0/1 (we don't care too much in U-Boot about taking a critical/mcheck inside another exception prolog/epilog). Also remove a few other small unused functions. Signed-off-by: NScott Wood <scottwood@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Scott Wood 提交于
Booke does not require exception vectors to be located at address zero. U-Boot was doing so anyway, simply because that's how it had been done on other PPC. The downside of this is that once the OS is loaded to address zero, the exception vectors have been overwritten -- which makes it difficult to diagnose a crash that happens after that point. The IVOR setup and trap entry code is simplified somewhat as a result. Also, there is no longer a need to align individual exceptions on 0x100 byte boundaries. Signed-off-by: NScott Wood <scottwood@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Shengzhou Liu 提交于
Support SODIMM D3XP12081XL10AA 1866MT/s on T2080RDB. Enable CONFIG_CMD_MEMTEST as well. Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Chunhe Lan 提交于
Now cortina driver uses macro CONFIG_SYS_CORTINA_FW_IN_NOR to define that firmware of cortina driver is stored in the nor flash. Signed-off-by: NChunhe Lan <Chunhe.Lan@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Ying Zhang 提交于
The fuse status register provides the values from on-chip voltage ID efuses programmed at the factory. These values define the voltage requirements for the chip. u-boot reads FUSESR and translates the values into the appropriate commands to set the voltage output value of an external voltage regulator. Signed-off-by: NYing Zhang <b40530@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Shengzhou Liu 提交于
T2080 rev1.1 also needs erratum a007186. Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Alexander Graf 提交于
QEMU 2.3 changes the address layout of the CCSR map in the PV ppce500 machine to reside in higher address space. Unfortunately, this exposed a glitch in u-boot for ppce500: While providing a function to dynamically evaluate the CCSR region's position in physical address space, we never used it. Plus we forgot to support 64bit physical addresses. This patch fixes that mishap, making u-boot work fine with latest QEMU again. Signed-off-by: NAlexander Graf <agraf@suse.de> Reviewed-by: NScott Wood <scottwood@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Curt Brune 提交于
According to the MPC8555/MPC8541 reference manual the SS_EN (source synchronous enable) bit in the DDR_SDRAM_CLK_CNLT register must be set during initialization. >From section 9.4.1.8 of that manual: Source synchronous enable. This bit field must be set during initialization. See Section 9.6.1, "DDR SDRAM Initialization Sequence," details. 0 - Reserved 1 - The address and command are sent to the DDR SDRAMs source synchronously. In addition, Freescale application note AN2805 is also very clear that this bit must be set. This patch reverts a change introduced by commit 457caecd. Testing Done: Compiled targets CONFIG_TARGET_MPC8555CDS and CONFIG_TARGET_MPC8541CDS and inspected the generated assembly code to verify the SS_EN bit was being set. There is one extra instruction emitted: fff9b774: 65 29 80 00 oris r9,r9,32768 Compiled the CONFIG_TARGET_MPC8548CDS target and verified that no additional instructions were emitted related to this patch. Booted an image on a MPC8541 based board successfully. Signed-off-by: NCurt Brune <curt@cumulusnetworks.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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- 20 4月, 2015 2 次提交
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由 Heiko Schocher 提交于
Signed-off-by: NHeiko Schocher <hs@denx.de>
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