- 25 1月, 2009 3 次提交
-
-
由 Dirk Behme 提交于
Add OMAP3, memory and function prototype header files for OMAP3. Signed-off-by: NDirk Behme <dirk.behme@googlemail.com>
-
由 Dirk Behme 提交于
Add pin mux, clock and cpu header files for OMAP3. Signed-off-by: NDirk Behme <dirk.behme@googlemail.com>
-
由 Maxim Artamonov 提交于
Signed-off-by: Maxim Artamonov <scn1874 at yandex.ru>
-
- 24 1月, 2009 37 次提交
-
-
-
-
由 Mike Frysinger 提交于
Some images can be quite large, so add an option to compress the image data with gzip in the U-Boot image. Then at runtime, the board can decompress it with the normal zlib functions. Signed-off-by: NMike Frysinger <vapier@gentoo.org>
-
由 Bryan Wu 提交于
A couple of buffers in the fat code are declared as an array of bytes. But it is then cast up to a structure with 16bit and 32bit members. Since GCC assumes structure alignment here, we have to force the buffers to be aligned according to the structure usage. Signed-off-by: NBryan Wu <bryan.wu@analog.com> Signed-off-by: NMike Frysinger <vapier@gentoo.org>
-
由 Brad Bozarth 提交于
Higher spi flash layers expect to be given back a pointer that was malloced so that it can free the result, but the lower layers return a pointer that is in the middle of the malloced memory. Reorder the members of the lower spi structures so that things work out. Signed-off-by: NBrad Bozarth <bflinux@yumbrad.com> Signed-off-by: NMike Frysinger <vapier@gentoo.org> Acked-by: NHaavard Skinnemoen <haavard.skinnemoen@atmel.com>
-
由 Yuri Tikhonov 提交于
When compile u-boot with the 2.18 binutils the following warning messages for each object file in post/lib_ppc/fpu/ is produced at the linking stage: post/libpost.a(acc1.o) uses hard float, u-boot uses soft-float ... This is because of the fact that, in general, the soft-float and hard-float ABIs are incompatible; the 2.18 binutils do checking of the Tag_GNU_Power_ABI_FP attribute of the files to be linked, and produce the worning like above if these are not compatible. The incompatibility of ABIs is concerned only the float values: e.g. the soft-float ABI assumes the float argument passing in the pair of rX registers, and the hard-float ABI assumes passing of the float argument in the fX register. When we don't pass the float arguments between the functions compiled with different floatness, then such an application will work correctly. This is the case for the FPU POST: u-boot (compiled with soft-float) doesn't pass to (and doesn't get from) the FPU POST functions any floats; there are no functions exported from the post/lib_ppc/fpu/ objects which would work with float parameters/returns too. So, we can reassure the linker not to worry about the difference in ABI attributes of linking files just by setting the 'soft-float' attribute for the objects in post/lib_ppc/fpu. And this patch does this. Also, to avoid passing both soft- and hard-float options in CFLAGS when compiling the files from post/lib_ppc/fpu (which is OK, but looks rather dirty) this patch removes the soft-float string from CFLAGS in post/lib_ppc/fpu/Makefile. Signed-off-by: NYuri Tikhonov <yur@emcraft.com>
-
由 Peter Tyser 提交于
Initial support for the DS4510, a CPU supervisor with integrated EEPROM, SRAM, and 4 programmable non-volatile GPIO pins. The CONFIG_DS4510 define enables support for the device while the CONFIG_CMD_DS4510 define enables the ds4510 command. The additional CONFIG_DS4510_INFO, CONFIG_DS4510_MEM, and CONFIG_DS4510_RST defines add additional sub-commands to the ds4510 command when defined. Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
-
由 Dirk Eibach 提交于
The iteration limit is passed to mtest as a fourth parameter: [start [end [pattern [iterations]]]] If no fourth parameter is supplied, there is no iteration limit and the test will loop forever. Signed-off-by: NDirk Eibach <eibach@gdsys.de>
-
由 Stefan Roese 提交于
Moved driver vcth.c to vct.c to better reflect the VCT board series. This driver is now used by the VCT platforms: vct_premium vct_platinum vct_platinumsvc Signed-off-by: NStefan Roese <sr@denx.de>
-
由 Shinya Kuribayashi 提交于
Signed-off-by: NShinya Kuribayashi <skuribay@ruby.dti.ne.jp>
-
由 Peter Korsgaard 提交于
Support bootdelay=0 in abortboot for the CONFIG_AUTOBOOT_KEYED case similar to the CONFIG_ZERO_BOOTDELAY_CHECK support for the !CONFIG_AUTOBOOT_KEYED case. Do this by reversing the loop so we do at least one iteration before checking for timeout. Signed-off-by: NPeter Korsgaard <jacmet@sunsite.dk>
-
由 Niklaus Giger 提交于
-
由 Graeme Russ 提交于
Signed-off-by: NGraeme Russ <graeme.russ@gmail.com>
-
由 Graeme Russ 提交于
Generic i386 reset - #define made redundant by weak function Signed-off-by: NGraeme Russ <graeme.russ@gmail.com>
-
由 Graeme Russ 提交于
CONFIG_SC520 is now used for conditional compile Signed-off-by: NGraeme Russ <graeme.russ@gmail.com>
-
由 Graeme Russ 提交于
Reset function specific to AMD SC520 microcontroller - Is more of a 'hard reset' that the triple fault. Requires CONFIG_SYS_RESET_SC520 to be defined in config I would have liked to add this to a new file (cpu/i386/sc520/reset.c) but ld requires that a object file in a library arhive MUST contain at least one function which does not override a weak function (and is called from outside the object file) in order for that object file to be extracted from the archive. This would be the only function on the new file, and hence, will never get linked in. Signed-off-by: NGraeme Russ <graeme.russ@gmail.com>
-
由 Graeme Russ 提交于
Moved from interrupts.c to cpu.c and made into a weak function to allow vendor specific override Vendor specific CPU reset (like the AMD SC520 MMCR reset) can now be added to the vendor specific code without the need to remember to #undef usage of the generic method and if you forget to include your custom reset method, you will always get the default. Signed-off-by: NGraeme Russ <graeme.russ@gmail.com>
-
由 Graeme Russ 提交于
This allows for future tidy ups and functionality that will require set_vector () Signed-off-by: NGraeme Russ <graeme.russ@gmail.com>
-
由 Graeme Russ 提交于
Signed-off-by: NGraeme Russ <graeme.russ@gmail.com> Signed-off-by: NWolfgang Denk <wd@denx.de>
-
由 Graeme Russ 提交于
Brings i386 in line with other CPUs with a reset vector and frees up reset.c for CPU reset functions Signed-off-by: NGraeme Russ <graeme.russ@gmail.com>
-
由 Wolfgang Denk 提交于
Signed-off-by: NWolfgang Denk <wd@denx.de>
-
由 Graeme Russ 提交于
Signed-off-by: NGraeme Russ <graeme.russ@gmail.com>
-
由 Kim Phillips 提交于
-
由 Gary Jennejohn 提交于
Right now this is only used by keymile. Signed-off-by: NGary Jennejohn <garyj@denx.de>
-
由 Heiko Schocher 提交于
This patch extracts the identical config options for the keymile boards mgcoge, mgsuvd and kmeter1 in a new common config file keymile-common.h. Signed-off-by: NHeiko Schocher <hs@denx.de>
-
由 Heiko Schocher 提交于
Check the presence of the PIGGY on the keymile boards mgcoge, mgsuvd and kmeter1. If the PIGGY is not present, dont register this Ethernet device. Signed-off-by: NHeiko Schocher <hs@denx.de> Acked-by: NBen Warren <biggerbadderben@gmail.com>
-
由 Heiko Schocher 提交于
This patch adds support for the kmeter1 board from Keymile, based on a Freescale MPC8360 CPU. - serial console on UART 1 - 256 MB DDR2 RAM - 64 MB NOR Flash - Ethernet RMII Mode over UCC4 - PHY SMSC LAN8700 Signed-off-by: NHeiko Schocher <hs@denx.de>
-
由 Sergei Poselenov 提交于
Add a do_div() wrapper, lldiv(). The new inline function doesn't modify the dividend and returns the result of division, so it is useful in complex expressions, i.e. "return(a/b)" -> "return(lldiv(a,b))" Signed-off-by: NSergei Poselenov <sposelenov@emcraft.com>
-
由 Kumar Gala 提交于
We move all IO addressed (CCSR, localbus, PCI) above the 4G boundary to allow for larger memory sizes. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Kumar Gala 提交于
The eLBC only handles 32-bit physical address in systems with 36-bit physical. The previos generation of LBC handled 34-bit physical address in 36-bit systems. Added a new CONFIG option to convey the difference between the LBC and eLBC. Also added defines for XAM bits used in LBC for the extended 34-bit support. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Kumar Gala 提交于
Use the new BR_ADDR macro to properly setup the address field of the localbus chipselects used by NAND. This allows us to deal with 36-bit phys on these boards in the future. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Haiying Wang 提交于
This patch updates e500 freqProcessor to array based on CONFIG_NUM_CPUS, and prints each CPU's frequency separately. It also fixes up each CPU's frequency in "clock-frequency" of fdt blob. Signed-off-by: NJames Yang <James.Yang@freescale.com> Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com>
-
由 Dave Liu 提交于
The wake up ARP feature need use the memory to process wake up packet, we enable auto self refresh to support it. Signed-off-by: NDave Liu <daveliu@freescale.com> Acked-by: NAndy Fleming <afleming@freescale.com>
-
由 Dave Liu 提交于
For light loaded system, we use the 1T timing to gain better memory performance, but for some heavily loaded system, you have to add the 2T timing options to board files. Signed-off-by: NDave Liu <daveliu@freescale.com> Acked-by: NAndy Fleming <afleming@freescale.com>
-
由 Dave Liu 提交于
Some 85xx processors have the advanced power management feature, such as wake up ARP, that needs enable the automatic self refresh. If the DDR controller pass the SR_IT (self refresh idle threshold) idle cycles, it will automatically enter self refresh. However, anytime one transaction is issued to the DDR controller, it will reset the counter and exit self refresh state. Signed-off-by: NDave Liu <daveliu@freescale.com> Acked-by: NAndy Fleming <afleming@freescale.com>
-
由 Dave Liu 提交于
- The DDR3 controller is expanding the bits for timing config - Add the DDR3 32-bit bus mode support Signed-off-by: NDave Liu <daveliu@freescale.com> Acked-by: NAndy Fleming <afleming@freescale.com>
-
由 Dave Liu 提交于
According to the latest 8572 UM, the DDR3 controller is expanding the bit mask, and we use the extend ACTTOPRE mode when tRAS more than 19 MCLK. Signed-off-by: NDave Liu <daveliu@freescale.com>
-