The mvsata_ide driver was due for DM conversion by v2019.07.  As that
has long passed, remove the driver and disable it in the boards which
had enabled it.
Signed-off-by: NTom Rini <trini@konsulko.com>

This board relies on using CONFIG_LIBATA but does not enable CONFIG_AHCI.  The
deadline for this conversion was the v2019.07 release.  The use of CONFIG_AHCI
requires CONFIG_DM.  The deadline for this conversion was v2020.01.  Remove
this board.
Signed-off-by: NTom Rini <trini@konsulko.com>

This board relies on using CONFIG_LIBATA but does not enable CONFIG_AHCI.  The
deadline for this conversion was the v2019.07 release.  In order to
convert to using the DWC SATA driver under DM further migrations are
required.

Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: NTom Rini <trini@konsulko.com>
Acked-by: NChristian Gmeiner <christian.gmeiner@gmail.com>

This board relies on using CONFIG_LIBATA but does not enable CONFIG_AHCI.  The
deadline for this conversion was the v2019.07 release.  The use of CONFIG_AHCI
requires CONFIG_DM.  The deadline for this conversion was v2020.01.  Remove
this board.

Cc: Akshay Bhat <akshaybhat@timesys.com>
Cc: Ken Lin <Ken.Lin@advantech.com.tw>
Signed-off-by: NTom Rini <trini@konsulko.com>

The dwc ahsata driver is written such that CONFIG_BLK must be enabled,
add this as a dependency in Kconfig.
Signed-off-by: NTom Rini <trini@konsulko.com>

Enable the AHCI and BLK features to complete migration of various
drivers.

Cc: Andrew F. Davis <afd@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: NTom Rini <trini@konsulko.com>

Signed-off-by: NTom Rini <trini@konsulko.com>

Add rt-thread art-pi board support based on STM32H750 SoC
Add Engicam i.Core STM32MP1 SoM
Add FIP header support for STM32programmer
Update uart number when no serial device found for STM32MP1
Remove board_check_usb_power function when ADC flag is not set
Update SPL size limitation for STM32MP1
Set soc_type, soc_pkg, soc_rev env variables for STM32MP1

u-boot-imx-20210409
-------------------

- Secure Boot :
	- HAB for MX8M / MX7ULP
	- CAAM fixes
- Fixes for imxrt1020
- Fixes for USDHC driver
- Fixes for Toradex (Colibri / Apalis)
- Switch to DM for several boards
	- mx23 olinuxo
	- usbarmory
	- marsboard / riotboard
	- Gateworks GW Ventana
- NXP upstream patches (LPDDR / CAAM / HAB)

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/7089

Split up get_soc_name(), clean the decoding up a bit, and set up
environment variables which contain the SoC type, package, revision.
This is useful on SoMs, where multiple SoC options are populated.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: NPatrick Delaunay <patrick.delaunay@foss.st.com>

A now removed comment promises to "limit SYSRAM usage to first 128 KB".
This would imply that only SYSRAM from 0x2ffc0000 - 0x2ffe0000 would be
used. This is not what happens at all.

First, SPL_MAX_SIZE is referenced from SPL_TEXT_BASE, which on all
existing configs is set to 0x2ffc2500, not SYSRAM_BASE (0x2ffc0000).
Some of it is in the first 128 KiB and some of it is in the second
128 KiB chunk of SYSRAM.

Second, SPL_MAX_SIZE, does not restrict the BSS size. While a valiant
attempt is made via SPL_BSS_MAX_SIZE, the value of 0x00100000 is much
larger than SYSRAM, and doesn't account for the non-BSS sections.

Because we're putting the .text and .bss in the same boat, the correct
way to limit them together is via SPL_MAX_FOOTPRINT. With the current
SPL_TEXT_BASE, we couldn't limit even a very basic SPL to the first
128 KiB, and there is no technical reason to do so. Because of this,
simply allow the SPL to use all SYSRAM.
Signed-off-by: NAlexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: NPatrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: NPatrick Delaunay <patrick.delaunay@foss.st.com>

CONFIG_SPL_BSS_START_ADDR is only used on a few mach- linker scripts.
stm32mp1 uses the generic script under arch/arm/cpu/u-boot-spl.lds,
which does not make use of this definition.

The SPL BSS starts in SRAM, right after .text, .rodata, .data, and
.u_boot_list. A very short version of the STM32MP1 memory map is:
  * SYSRAM: 2ffc0000 - 30000000     <- all of SPL is here
  * DRAM:   c0000000+

0xC0200000 is a DRAM address, and has nothing to do with SPL. It is
just very misleading to have it next to CONFIG_SPL_BSS_MAX_SIZE, or to
have it at all.
Signed-off-by: NAlexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: NPatrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: NPatrick Delaunay <patrick.delaunay@foss.st.com>

Since commit 03f1f78a ("spl: fit: Prefer a malloc()'d buffer for
loading images"), FIT images must be malloc()'d before being loaded.
The old size of 1 MiB is suitable for FIT images with u-boot and an
FDT, but something containing a linux kernel is almost sure to fail.

It's safe to extend malloc all the way to 0xc2000000, but no further.
Linux likes to be loaded at 0xc2000000, so we use that as our cutoff
point. This gives us 29 MiB of malloc() space, which suited for more
complex FIT images including several DTBs, kernel, and OP-TEE images.
Signed-off-by: NAlexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: NPatrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: NPatrick Delaunay <patrick.delaunay@foss.st.com>

Simplify the code of the function board_check_usb_power
based in CONFIG_ADC and adc_measurement; the function is removed by the
linker when the CONFIG_ADC is not activated.
Signed-off-by: NPatrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: NPatrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>

Replace the remaining printf in setup_boot_mode() by log macro
to handle filtering for log features.
Signed-off-by: NPatrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: NPatrice Chotard <patrice.chotard@foss.st.com>

Align the uart number in the trace of setup_boot_mode() with the name of
the uart/usart device (start at 1) and not with the instance value
(start at 0), i.e. the serial device sequence number and the index in
serial_addr[].

Fixes: f49eb16c ("stm32mp: stm32prog: replace alias by serial
device sequence number")
Signed-off-by: NPatrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: NPatrice Chotard <patrice.chotard@foss.st.com>

Add support of TF-A FIP header in command stm32prog for all the boot
partition and not only the STM32IMAGE.

This patch is a preliminary patch to support FIP as second boot stage
after TF-A BL2 when CONFIG_TFABOOT is activated for trusted boot chain.

The FIP is archive binary loaded by TF-A BL2, which contains the secure OS
= OP-TEE and the non secure firmware and device tree = U-Boot.
Signed-off-by: NPatrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: NPatrice Chotard <patrice.chotard@foss.st.com>

7" OF is a capacitive touch 7" Open Frame panel solutions with
- 7" AUO B101AW03 LVDS panel
- EDT, FT5526 Touch

MicroGEA STM32MP1 is a STM32MP157A based Micro SoM.

MicroDev 2.0 is a general purpose miniature carrier board with CAN,
LTE and LVDS panel interfaces.

MicroGEA STM32MP1 needs to mount on top of MicroDev 2.0 board with
pluged 7" OF for creating complete MicroGEA STM32MP1 MicroDev 2.0
7" Open Frame Solution board.

Linux dts commit details:

commit <1d278204cbaa> ("ARM: dts: stm32: Add Engicam MicroGEA STM32MP1
MicroDev 2.0 7" OF")

Add support for it.
Reviewed-by: NPatrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: NPatrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>

MicroDev 2.0 is a general purpose miniature carrier board with CAN,
LTE and LVDS panel interfaces.

Genaral features:
- Ethernet 10/100
- USB Type A
- Audio Out
- microSD
- LVDS panel connector
- Wifi/BT (option)
- UMTS LTE with sim connector (option)

MicroGEA STM32MP1 is a STM32MP157A based Micro SoM.

MicroGEA STM32MP1 needs to mount on top of this MicroDev 2.0 board
for creating complete MicroGEA STM32MP1 MicroDev 2.0 Carrier board.

Linux dts commit details:

commit <f838dae7afd0> ("ARM: dts: stm32: Add Engicam MicroGEA STM32MP1
MicroDev 2.0 board")

Add support for it.
Reviewed-by: NPatrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>

MicroGEA STM32MP1 is a STM32MP157A based Micro SoM.

General features:
- STM32MP157AAC
- Up to 1GB DDR3L-800
- 512MB Nand flash
- I2S

MicroGEA STM32MP1 needs to mount on top of Engicam MicroDev carrier
boards for creating complete platform solutions.

Linux dts commit details:

commit <0be81dfaeaf8> ("ARM: dts: stm32: Add Engicam MicroGEA STM32MP1
SoM")

Add support for it.
Reviewed-by: NPatrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: NPatrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>

Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier
board.

Genaral features:
- Ethernet 10/100
- Wifi/BT
- USB Type A/OTG
- Audio Out
- CAN
- LVDS panel connector

i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.

i.Core STM32MP1 needs to mount on top of this Carrier board for
creating complete i.Core STM32MP1 C.TOUCH 2.0 board.

Linux dts commit details:

commit <6ca2898df59f> ("ARM: dts: stm32: Add Engicam i.Core STM32MP1
C.TOUCH 2.0")

Add support for it.
Reviewed-by: NPatrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: NPatrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>

Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive
Evaluation Board.

Genaral features:
- LCD 7" C.Touch
- microSD slot
- Ethernet 1Gb
- Wifi/BT
- 2x LVDS Full HD interfaces
- 3x USB 2.0
- 1x USB 3.0
- HDMI Out
- Mini PCIe
- MIPI CSI
- 2x CAN
- Audio Out

i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.

i.Core STM32MP1 needs to mount on top of this Evaluation board for
creating complete i.Core STM32MP1 EDIMM2.2 Starter Kit.

Linux dts commit details:

commit <adc0496104b6> ("ARM: dts: stm32: Add Engicam i.Core STM32MP1
EDIMM2.2 Starter Kit")

Add support for it.
Reviewed-by: NPatrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>

SPI Load isn't mandatory for STM32 builds.

Let's imply instead of select it to get rid of build
issues for non-SPI defconfigs.
Reviewed-by: NPatrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: NPatrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>

Engicam i.Core STM32MP1 SODIMM SoM has mounted 1x4Gb DDR3
which has 32bits width 528000Khz frequency.

Add DDR configuration via dtsi.
Reviewed-by: NPatrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: NPatrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>

i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.

General features:
- STM32MP157A
- Up to 1GB DDR3L
- 4GB eMMC
- 10/100 Ethernet
- USB 2.0 Host/OTG
- I2S
- MIPI DSI to LVDS
- rest of STM32MP157A features

i.Core STM32MP1 needs to mount on top of Engicam baseboards
for creating complete platform solutions.

Linux commit details:

commit <30f9a9da4ee1> ("ARM: dts: stm32: Add Engicam i.Core STM32MP1
SoM")

Add support for it.
Reviewed-by: NPatrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: NPatrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>

All these files are add for support rt-thread art-pi board
- add board/st/stm32h750-art-pi, defconfig, header support for u-boot

for more information about art-pi, please goto:
https://art-pi.gitee.io/website/Signed-off-by: Ndillon min <dillon.minfei@gmail.com>
Reviewed-by: NPatrice Chotard <patrice.chotard@foss.st.com>

strsep will change data from original memory address,
in case the memory is in non-sdram/sram place, will
run into a bug(hang at SDRAM: )

just add a temporary array to store bank_name[] to fix this
bug.
Signed-off-by: Ndillon min <dillon.minfei@gmail.com>
Reviewed-by: NPatrice Chotard <patrice.chotard@foss.st.com>

This patchset has following changes:

- introduce stm32h750.dtsi to support stm32h750 value line
- add pin groups for usart3/uart4/spi1/sdmmc2
- add stm32h750i-art-pi.dtb (arch/arm/boot/dts/Makefile)
- add stm32h750i-art-pi.dts to support art-pi board
- add stm32h750i-art-pi-u-boot.dtsi to support art-pi board (u-boot)

art-pi board component:
- 8MiB qspi flash
- 16MiB spi flash
- 32MiB sdram
- ap6212 wifi&bt&fm

the detail board information can be found at:
https://art-pi.gitee.io/website/Signed-off-by: Ndillon min <dillon.minfei@gmail.com>
Reviewed-by: NPatrice Chotard <patrice.chotard@foss.st.com>

Replace upper case by lower case in i2c nodes name.
update dmamux1 register range.
Signed-off-by: Ndillon min <dillon.minfei@gmail.com>
Reviewed-by: NPatrice Chotard <patrice.chotard@foss.st.com>

Some instances are missing in current support of stm32h743 MCU. This commit
adds usart3/uart4 and sdmmc2 support.
Signed-off-by: Ndillon min <dillon.minfei@gmail.com>
Reviewed-by: NPatrice Chotard <patrice.chotard@foss.st.com>

This patch is intend to add support stm32h750 value line,
just add stm32h7-pinctrl.dtsi for extending, with following changes:

- rename stm32h743-pinctrl.dtsi to stm32h7-pinctrl.dtsi
- move 'pin-controller' from stm32h7-pinctrl.dtsi to stm32h743.dtsi
- update stm32h743i-{disco, eval}.dts to include stm32h7-pinctrl.dtsi
Signed-off-by: Ndillon min <dillon.minfei@gmail.com>
Reviewed-by: NPatrice Chotard <patrice.chotard@foss.st.com>

As different boards has their own sdram hw connection, mount different
sdram modules, so move sdram timing parameter and pin configuration
to their board device tree.
Signed-off-by: Ndillon min <dillon.minfei@gmail.com>
Reviewed-by: NPatrice Chotard <patrice.chotard@foss.st.com>

This reverts the arch/arm/mach-imx/imx_bootaux.c changes of commit
805b3cac. The loader function name was changed so that it does
not clash with the generically available function in lib/elf.c.

imx-bootaux loads an elf file linked for an auxilary core. Thus the
loader function requires address translation from the auxilary core's
address space to where those are mapped into U-Boot's address space.

So the elf loader is specific and must not be replaced with a generic
loader which doesn't provide the address translation functionality.

Fixes commit 805b3cac ("lib: elf: Move the generic elf
loading/validating functions to lib")
Signed-off-by: NMax Krummenacher <max.krummenacher@toradex.com>
Acked-by: NOleksandr Suvorov <oleksandr.suvorov@toradex.com>

Pass "pfuze3000@8" in pmic_get() so that the PMIC node can
be found in the devicetree.
Signed-off-by: NFabio Estevam <festevam@gmail.com>
Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>

Some board like imx8mm-evkb, IO voltage switch from 3.3v to 1.8v need
around 18ms, common code only delay 10ms, so need to delay extra 8ms.
Otherwise voltage switch will timeout when wait for data0 line.

This IO voltage switch time depends on board design, depend on the
PMIC and capacitance. imx8mm-evkb board use PCA9450(PMIC) and 10uF
capacitance.
Signed-off-by: NHaibo Chen <haibo.chen@nxp.com>

Common code already handle the voltage switch sequence based on spec,
so remove the redundant voltage switch code.
Signed-off-by: NHaibo Chen <haibo.chen@nxp.com>

Bitmap files should not be executable.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: NMichael Trimarchi <michael@amarulasolutions.com>

sel_input value for the following uart5 pins is
different between i.MX6UL and i.MX6ULL:

MX6_PAD_UART5_TX_DATA__UART5_DTE_RX
MX6_PAD_UART5_RX_DATA__UART5_DCE_RX
MX6_PAD_ENET1_RX_EN__UART5_DCE_RTS
MX6_PAD_ENET1_TX_DATA0__UART5_DTE_RTS
MX6_PAD_CSI_DATA02__UART5_DCE_RTS

As sel_input value for the second one is fixed by
the previous commit, fix the rest.
Signed-off-by: NYuichiro Goto <goto@k-tech.co.jp>

Document SRC_GPR10 PERSIST_SECONDARY_BOOT functionality. This is useful for
reliable bootloader A/B updates, as it permits switching between two copies
of bootloader at different offsets of the same storage. The switch happens
in case one copy is corrupted OR can be enforced by user. This functionality
is present at least since i.MX53, however is poorly documented in all known
SoC datasheets, hence this document aims to clarify the usage, currently on
i.MX7D and i.MX8MM.

Signed-off-by: Marek Vasut <marex@denx.de> # Original MX7D work, this document
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io> # All the MX8M work
Cc: Christoph Niedermaier <cniedermaier@dh-electronics.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Harald Seiler <hws@denx.de>
Cc: Igor Opaniuk <igor.opaniuk@foundries.io>
Cc: Jan Kiszka <jan.kiszka@siemens.com>
Cc: Ludwig Zenz <lzenz@dh-electronics.com>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
Reviewed-by: NPeng Fan <peng.fan@nxp.com>