- 01 7月, 2020 24 次提交
-
-
由 Sean Anderson 提交于
The Sipeed Maix series is a collection of boards built around the RISC-V Kendryte K210 processor. This processor contains several peripherals to accelerate neural network processing and other "ai" tasks. This includes a "KPU" neural network processor, an audio processor supporting beamforming reception, and a digital video port supporting capture and output at VGA resolution. Other peripherals include 8M of sram (accessible with and without caching); remappable pins, including 40 GPIOs; AES, FFT, and SHA256 accelerators; a DMA controller; and I2C, I2S, and SPI controllers. Maix peripherals vary, but include spi flash; on-board usb-serial bridges; ports for cameras, displays, and sd cards; and ESP32 chips. Currently, only the Sipeed Maix Bit V2.0 (bitm) is supported, but the boards are fairly similar. Documentation for Maix boards is located at <http://dl.sipeed.com/MAIX/HDK/>. Documentation for the Kendryte K210 is located at <https://kendryte.com/downloads/>. However, hardware details are rather lacking, so most technical reference has been taken from the standalone sdk located at <https://github.com/kendryte/kendryte-standalone-sdk>. Signed-off-by: NSean Anderson <seanga2@gmail.com>
-
由 Sean Anderson 提交于
This patch adds documentation for the Sipeed Maix bit, and more generally for the Kendryte K210 processor. Signed-off-by: NSean Anderson <seanga2@gmail.com>
-
由 Sean Anderson 提交于
Where possible, I have tried to find compatible drivers based on the layout of registers. However, many devices remain untested. All untested devices have been left disabled, but some tentative properties (such as compatible strings, and clocks, interrupts, and resets properties) have been added. Signed-off-by: NSean Anderson <seanga2@gmail.com>
-
由 Sean Anderson 提交于
The cpu clock is probably already enabled if we are executing code (though we could be executing from a different core). This patch prevents the cpu clock or its parents from being disabled. Signed-off-by: NSean Anderson <seanga2@gmail.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
-
由 Sean Anderson 提交于
Instead of always using the "clock-frequency" property to determine cpu frequency, try using a clock in "clocks" if it exists. This patch also fixes a bug where there could be spurious higher frequencies if sizeof(u32) != sizeof(ulong). Signed-off-by: NSean Anderson <seanga2@gmail.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
-
由 Sean Anderson 提交于
Currently, one cannot use a reset driver on RISC-V. Follow the MIPS example, and disable the default reset handler when the sysreset driver is enabled. Signed-off-by: NSean Anderson <seanga2@gmail.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
-
由 Sean Anderson 提交于
Some older processors (notably the Kendryte K210) use an older version of the RISC-V privileged specification. The primary changes between the old and new are in virtual memory, and in the merging of three separate counter enable CSRs. Using the new CSR on an old processor causes an illegal instruction exception. This patch adds an option to use the old CSRs instead of the new one. Signed-off-by: NSean Anderson <seanga2@gmail.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
-
由 Sean Anderson 提交于
The previous IPI code initialized the device whenever the first call was made to a riscv_*_ipi function. This made it difficult to determine when the IPI device was initialized. This patch introduces a new function riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions should be called. Signed-off-by: NSean Anderson <seanga2@gmail.com> Reviewed-by: NRick Chen <rick@andestech.com>
-
由 Sean Anderson 提交于
On some platforms (k210), the previous stage bootloader may have not cleared pending IPIs before transferring control to U-Boot. This can cause race conditions, as multiple harts all attempt to initialize the IPI controller at once. This patch clears IPIs before enabling them, ensuring that only one hart modifies shared memory at once. Signed-off-by: NSean Anderson <seanga2@gmail.com> Reviewed-by: NRick Chen <rick@andestech.com>
-
由 Sean Anderson 提交于
This header depended on bd_t and ulong, but did not include the appropriate headers. Signed-off-by: NSean Anderson <seanga2@gmail.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
-
由 Sean Anderson 提交于
This could give a confusing error message if it failed and didn't set errno. Signed-off-by: NSean Anderson <seanga2@gmail.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
-
由 Sean Anderson 提交于
This patch adds a generic reset driver. It is designed to be useful when one has a register in a regmap which contains bits that reset other devices. I thought this seemed like a very generic use, so here is a generic driver. The overall structure has been modeled on the syscon-reboot driver. Signed-off-by: NSean Anderson <seanga2@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
-
由 Sean Anderson 提交于
dev_read_addr_ptr had different semantics depending on whether OF_LIVE was enabled. This patch converts both implementations to return NULL on error, and converts all call sites which check for FDT_ADDR_T_NONE to check for NULL instead. This patch also removes the call to map_physmem, since we have dev_remap_addr* for those semantics. Signed-off-by: NSean Anderson <seanga2@gmail.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
-
由 Sean Anderson 提交于
This type of bus is used in Linux to designate buses which have power domains and/or clocks which need to be enabled before their child devices can be used. Because power domains are automatically enabled before probing in U-Boot, we just need to enable any clocks present. Signed-off-by: NSean Anderson <seanga2@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
-
由 Sean Anderson 提交于
Due to the large number of clocks, I decided to use the CCF. The overall structure is modeled after the imx code. Clocks parameters are stored in several arrays, and are then instantiated at run-time. There are some translation macros (FOOIFY()) which allow for more dense packing. Signed-off-by: NSean Anderson <seanga2@gmail.com> CC: Lukasz Majewski <lukma@denx.de>
-
由 Sean Anderson 提交于
This is a small driver to do a software bypass of a clock if hardware bypass is not working. I have tried to write this in a generic fashion, so that it could be potentially broken out of the kendryte code at some future date. For the K210, it is used to have aclk bypass pll0 and use in0 instead so that the CPU keeps on working. Signed-off-by: NSean Anderson <seanga2@gmail.com> CC: Lukasz Majewski <lukma@denx.de>
-
由 Sean Anderson 提交于
This pll code is primarily based on the code from the kendryte standalone sdk in lib/drivers/sysctl.c. k210_pll_calc_config is roughly analogous to the algorithm used to set the pll frequency, but it has been completely rewritten to be fixed-point based. Signed-off-by: NSean Anderson <seanga2@gmail.com> CC: Lukasz Majewski <lukma@denx.de>
-
由 Sean Anderson 提交于
clk_get_by_index_nodev only ever fetched clock 1, due to passing a boolean predicate instead of the index. Other clk_get_by_* functions got the clock correctly, but passed a predicate instead of the index to clk_get_by_tail. This could lead to confusing error messages. Signed-off-by: NSean Anderson <seanga2@gmail.com> CC: Lukasz Majewski <lukma@denx.de>
-
由 Sean Anderson 提交于
clk_composite_ops was shared between all devices in the composite clock driver. If one clock had a feature (such as supporting set_parent) which another clock did not, it could call a null pointer dereference. This patch does three things 1. It adds null-pointer checks to all composite clock functions. 2. It makes clk_composite_ops const and sets its functions at compile-time. 3. It adds some basic sanity checks to num_parents. The combined effect of these changes is that any of mux, rate, or gate can be NULL, and composite clocks will still function normally. Previously, at least mux had to exist, since clk_composite_get_parent was used to determine the parent for clk_register. Signed-off-by: NSean Anderson <seanga2@gmail.com> Acked-by: NLukasz Majewski <lukma@denx.de>
-
由 Sean Anderson 提交于
CCF clocks should always use the struct clock passed to their methods for extracting the driver-specific clock information struct. Previously, many functions would use the clk->dev->priv if the device was bound. This could cause problems with composite clocks. The individual clocks in a composite clock did not have the ->dev field filled in. This was fine, because the device-specific clock information would be used. However, since there was no ->dev, there was no way to get the parent clock. This caused the recalc_rate method of the CCF divider clock to fail. One option would be to use the clk->priv field to get the composite clock and from there get the appropriate parent device. However, this would tie the implementation to the composite clock. In general, different devices should not rely on the contents of ->priv from another device. The simple solution to this problem is to just always use the supplied struct clock. The composite clock now fills in the ->dev pointer of its child clocks. This allows child clocks to make calls like clk_get_parent() without issue. imx avoided the above problem by using a custom get_rate function with composite clocks. Signed-off-by: NSean Anderson <seanga2@gmail.com> Acked-by: NLukasz Majewski <lukma@denx.de>
-
由 Tom Rini 提交于
- Minor updates to some platforms I am the listed maintainer of. Notably this removes the ti814x_evm which stopped building with the PXA MMC migration series (oops) but hasn't been functional in some time.
-
由 Tom Rini 提交于
The TI814x (DM814x) platform is rather old and in need of a lot of migration work. As much of that work is well past the deadline, remove this platform. Signed-off-by: NTom Rini <trini@konsulko.com>
-
由 Tom Rini 提交于
This platform is already using DM in general and the MMC controller is the early generation of what is compatible with "ti,omap4-hsmmc" so enable DM_MMC (which in turn gets BLK enabled). Signed-off-by: NTom Rini <trini@konsulko.com>
-
由 Tom Rini 提交于
Both the am335x_boneblack and am335x_evm_usbspl configs have been gone for a while, remove their entries from MAINTAINERS. Signed-off-by: NTom Rini <trini@konsulko.com>
-
- 30 6月, 2020 16 次提交
-
-
https://gitlab.denx.de/u-boot/custodians/u-boot-mips由 Tom Rini 提交于
- net: pcnet: cleanup and add DM support - Makefile: add rule to build an endian-swapped U-Boot image used by MIPS Malta EL variants - CI: add Qemu tests for MIPS Malta
-
由 Tom Rini 提交于
- Migrate the PXA MMC driver to driver model.
-
由 Marcel Ziswiler 提交于
Enable CONFIG_DM_MMC. Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com> Reviewed-by: NIgor Opaniuk <igor.opaniuk@toradex.com>
-
由 Marcel Ziswiler 提交于
Add MMC platform data. While at it also fix trivial checkpatch.pl issues. Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com>
-
由 Marcel Ziswiler 提交于
Enable CONFIG_CMD_DM. Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com>
-
由 Marcel Ziswiler 提交于
Add driver model (DM) support. Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com>
-
由 Marcel Ziswiler 提交于
Move CONFIG_PXA_MMC_GENERIC to Kconfig. Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
-
由 Marcel Ziswiler 提交于
Gracefully handle alias seq in the platform data rather than OF case. Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com>
-
由 Marcel Ziswiler 提交于
Allow for CONFIG_DM_MMC with platform data rather than CONFIG_OF_CONTROL. Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com>
-
由 Marcel Ziswiler 提交于
Clean-up platform data include file by using BIT macro and converting indentation with spaces to tabs. Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com>
-
由 Marcel Ziswiler 提交于
Add missing space before a comment delimiter. Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com> Reviewed-by: NPeng Fan <peng.fan@nxp.com> Reviewed-by: NIgor Opaniuk <igor.opaniuk@toradex.com>
-
由 Daniel Schwierzeck 提交于
Add Qemu tests for the MIPS Malta machine as a replacement for the deprecated generic MIPS machine. Signed-off-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
-
由 Daniel Schwierzeck 提交于
Add Qemu tests for the MIPS Malta machine as a replacement for the deprecated generic MIPS machine. Signed-off-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
-
由 Daniel Schwierzeck 提交于
Add Qemu tests for the MIPS Malta machine as a replacement for the deprecated generic MIPS machine. Signed-off-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
-
由 Daniel Schwierzeck 提交于
The Qemu Malta machine expects the firmware in Big-Endian byte order. Therefore the Little-Endian variants of the Malta board needs to be byte swapped. Signed-off-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
-
由 Daniel Schwierzeck 提交于
This rule generates an u-boot binary file where the byte endianness is swapped. This will be used by the MIPS Malta Little-Endian variants to be able to boot with Qemu. The Qemu Malta Machine expects the firmware in Big-Endian order. Signed-off-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
-