Align the output for PCI. Replace "PCI" with "PCI1".
Signed-off-by: NZhao Chenhui <chenhui.zhao@freescale.com>

Pre u-boot Flow:
1. User loads the u-boot image in flash
2. PBL/Configuration word is used to create LAW for Flash at 0xc0000000
   (Please note that ISBC expects all these addresses, images to be
    validated, entry point etc within 0 - 3.5G range)
3. ISBC validates the u-boot image, and passes control to u-boot
   at 0xcffffffc.

Changes in u-boot:
1. Temporarily map CONFIG_SYS_MONITOR_BASE to the 1M
   CONFIG_SYS_PBI_FLASH_WINDOW in AS=1.
   (The CONFIG_SYS_PBI_FLASH_WINDOW is the address map for the flash
    created by PBL/configuration word within 0 - 3.5G memory range. The
    u-boot image at this address has been validated by ISBC code)
2. Remove TLB entries for 0 - 3.5G created by ISBC code
3. Remove the LAW entry for the CONFIG_SYS_PBI_FLASH_WINDOW created by
   PBL/configuration word after switch to AS = 1
Signed-off-by: NRuchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: NKuldip Giroh <kuldip.giroh@freescale.com>
Acked-by: NWood Scott-B07421 <B07421@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Signed-off-by: NRuchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: NKuldip Giroh <kuldip.giroh@freescale.com>

Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

CPLD 2.2 removed board watch dog support due to the limitation of CPLD
capacity after adding all the requested features, such as switch overriding.
There is no pin-compatible upgrade part available for current PCB design.
So remove codes related to it.
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

According to CPLD 2.2, the default configuration is changed, so updated the
description of CPLD command, otherwise it will confusing.
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

This table covers DDR frequencies from 666 to 1666. Frequencies 666, 833,
1000, 1066 and 1333 were verified on this board with SO-DIMM
(UG51U6400N8SU-ACF).
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

P2041RDB supports 3 sysclk frequencies, it's selected by SW1[6~8],
software need to read the SW1 status to decide what the sysclk needs.

SW1[8~6] : frequency
0 0 1 : 83.3MHz
0 1 0 : 100MHz
others: 66.667MHz
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

CPLD 2.0 provides a new register which bit[0] is set to '1' will reset
board with initializing the CPLD registers to default values. And add
bit[6] of register at offset 0x5 to use to enable flash bank selection.
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Update MPC8349EMDS to use unified DDR driver instead of spd_sdram.c.
The unified driver can initialize data using DDR controller. No need to
use DMA if just to initialze for ECC.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Unified DDR driver is maintained for better performance, robustness and bug
fixes. Upgrading to use unified DDR driver for MPC83xx takes advantage of
overall improvement. It requires changes for board files to customize
platform-dependent parameters.

To utilize the unified DDR driver, a board needs to define CONFIG_FSL_DDRx
in the header file. No more boards will be accepted without such definition.

Note: the workaround for erratum DDR6 for the very old MPC834x Rev 1.0/1.1
and MPC8360 Rev 1.1/1.2 parts is not migrated to unified driver.
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

DDR2 has different ODT table and values. Adding table according to Samsung
application note.

Fix additive latency calculation to avoid interger underflow.

Also converted typedef dynamic_odt_t to struct dynamic_odt.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Reduce the calculation error to 1ps.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The two slots on the same controller have different addresses.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Check second DIMM slot in case the first one is empty.
Honor DQS enable option for SDRAM mode register.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The P2041RDB has almost identical setup for TLB, LAWS, and PCI with
other P-Series CoreNet platforms.

The only difference between P2041RDB & P3041DS/P4080DS/P5020DS is the
CPLD vs PIXIS FPGA which we can handle via some simple #ifdefs in the
TLB and LAW setup tables.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

We currently support 4 SoC/Boards from the P-Series of QorIQ SoCs that
are based on the 'CoreNet' Architecture: P2041RDB, P3041DS, P4080DS, and
P5020DS.  There is a significant amount of commonality shared between
these boards that we can refactor into common code:

* Initial LAW setup
* Initial TLB setup
* PCI setup

We start by moving the shared code between P3041DS, P4080DS, and P5020DS
into a common directory to be shared with other P-Series CoreNet boards.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Useful for various debug to know how various regsters might be set
in a human readable form.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

We shouldn't be setting execute permissions on TLB entries that will not
actually have any code run from them.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

USB protocol macros (CONFIG_USB_EHCI ...) to be included only when
CONFIG_HAS_FSL_DR_USB is defined for a board. Presence of USB DR controller
should be declared along with the underlying protocol used in the controller
Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

RDIMM has different timing parameters from UDIMM. Create new tables for
RDIMMs. Single-, dual- and quad-rank RDIMMs have been verified with speeds
from 800 to 1333MT/s. Speed table expands to include 1600MT/s for future
use. Single- and quad-rank RDIMM entries are copied into UDIMM tables for
future use.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

DDR RCW varies at different speeds. It is common for all platform. Move it
out from corenet_ds.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Extend CAS write Latency (CWL) table to comply with DDR3 spec
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The MPC8536 seems to use only 3 bits for the major revision field in the
SVR rather than the 4 bits used by all other processors.  The most
significant bit is used as a mfg code on MPC8536.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Move extern of pci_of_setup() into corenet_ds.h
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Add support for RGMII, SGMII and XAUI Ethernet on P2041RDB board.

The five dTSEC can be routed to two on-board RGMII phy, three on-board
SGMII phy or four SGMII phy on SGMII riser card according to different
serdes protocol configuration and board lane configuration. Also updated
the device tree to direct the Fmac MAC to the correct PHY.

Removed CONFIG_SYS_FMAN_FW as its not used anywhere.
Signed-off-by: NMingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The P1023 has two 1G ethernet controllers the first can run in
SGMII, RGMII, or RMII.  The second can only do SGMII & RGMII.

We need to setup a for SoC & board registers based on our various
configuration for ethernet to function properly on the board.

Removed CONFIG_SYS_FMAN_FW as its not used anywhere.
Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com>
Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: NLei Xu <B33228@freescale.com>
Signed-off-by: NIoana Radulescu <ruxandra.radulescu@freescale.com>
Signed-off-by: NShaohui Xie <b21989@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Add support for RGMII, SGMII, and XAUI (10Gb) Ethernet on P3041DS &
P5020DS ("Hydra").

The lane_to_slot[] array is initialized dynamically, since board switches
can be used to control the muxing of SERDES lanes to slots.

The BRDCFG1 PIXIS register is used to route the MII bus to the appropriate
slot.  The SERDES configuration is queried to help determine the routing
between MACs and slot/phy combination.

If a XAUI card is inserted, muxing for that card is enabled and never
turned off.  The PHY address for the 10G XAUI card depends on the slot in
which it's inserted.  If it's in slot 1, the address is 4.  If it's in
slot 2, the address is 0.

Update the MDIO routing in the P3041DS and P5020DS device trees based on
the board-level muxing.  The SERDES configuration determines which
SGMII/XGMII boards are located in which slots, and so the MDIO bus needs
to be muxed correctly whenever talking to a PHY connected to any Fman MAC.
The Fman Ethernet nodes in the device tree also need to be routed to the
correct PHYs.

Removed CONFIG_SYS_FMAN_FW as its not used anywhere.
Signed-off-by: NIoana Radulescu <ruxandra.radulescu@freescale.com>
Signed-off-by: NTimur Tabi <timur@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Add support for RGMII, SGMII, and XAUI (10Gb) Ethernet on P4080DS.

The board supports add-on cards for SGMII and XAUI functionality.  Which
slots on the board these cards are in is a function of the SERDES option
selected and muxes on the board.

Additionally because of the high-configurablity which MDIO bus one is
connected to is "selected" via an FPGA register.  We create dummy MDIO
bus for the phy layer and hide the mux manipulation in this dummy layer.

Add fman fdt helper function in board common code it'll be used by several
freescale boards that do various muxing of the MDIO signals based on which
controller/interface one is trying to talk to.

Removed CONFIG_SYS_FMAN_FW as its not used anywhere.
Signed-off-by: NMingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>
Signed-off-by: NTimur Tabi <timur@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The Frame Manager (FMan) on QorIQ SoCs with DPAA (datapath acceleration
architecture) is the ethernet contoller block.  Normally it is utilized
via Queue Manager (Qman) and Buffer Manager (Bman).  However for boot
usage the FMan supports a mode similar to QE or CPM ethernet collers
called Independent mode.

Additionally the FMan block supports multiple 1g and 10g interfaces as a
single entity in the system rather than each controller being managed
uniquely.  This means we have to initialize all of Fman regardless of
the number of interfaces we utilize.

Different SoCs support different combinations of the number of FMan as
well as the number of 1g & 10g interfaces support per Fman.

We add support for the following SoCs:
 * P1023 - 1 Fman, 2x1g
 * P4080 - 2 Fman, each Fman has 4x1g and 1x10g
 * P204x/P3041/P5020 - 1 Fman, 5x1g, 1x10g
Signed-off-by: NDave Liu <daveliu@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>
Signed-off-by: NTimur Tabi <timur@freescale.com>
Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com>
Signed-off-by: NDai Haruki <dai.haruki@freescale.com>
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
Signed-off-by: NIoana Radulescu <ruxandra.radulescu@freescale.com>
Signed-off-by: NLei Xu <B33228@freescale.com>
Signed-off-by: NMingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: NScott Wood <scottwood@freescale.com>
Signed-off-by: NShaohui Xie <b21989@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Remove unnecessary or dead code/includes.
Signed-off-by: NZhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Some SOCs have discontiguously-numbered cores, and so we can't determine the
valid core numbers via the FRR register any more.  We define
CPU_TYPE_ENTRY_MASK to specify a discontiguous core mask, and helper functions
to process the mask and enumerate over the set of valid cores.
Signed-off-by: NTimur Tabi <timur@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

We shouldn't be setting execute permissions on TLB entries that will not
actually have any code run from them.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Add a helper function that will return a phandle value for the given
node.  If the node doesn't have a phandle already one will be created.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
Acked-by: NGerald Van Baren <vanbaren@cideas.com>

The old fdt_create_phandle didn't actually create a phandle it just
set one.  We'll introduce a new helper that actually does creation.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
Acked-by: NGerald Van Baren <vanbaren@cideas.com>

Add ifdef protection around fman specific code related to device tree
clock setup.  If we dont have CONFIG_SYS_DPAA_FMAN defined we shouldn't
be executing this code.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Issue: Address masking doesn't work properly.
When sum of the base address, defined by BA, and memory bank size,
defined by AM, exceeds 4GB (0xffff_ffff) then AMASKn[AM] doesn't mask
CSPRn[BA] bits.

Impact:
This will impact booting when we are reprogramming CSPR0(BA) and
AMASK0(AMASK) while executing from NOR Flash.

Workaround:
Re-programming of CSPR(BA) and AMASK is done while not executing from NOR
Flash. The code which programs the BA and AMASK is executed from L2-SRAM.
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Issue:
Peripheral connected to IFC_CS3 may hamper booting from IFC.

Impact:
Boot from IFC may not be successful if IFC_CS3 is used.

Workaround:
If IFC_CS3 is used, gate IFC_CS3 while booting from NAND or NOR.
Also Software should select IFC_CS3 using PMUXCR[26:27] = 0x01.
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Issue:
The NOR-FCM does not support access to unaligned addresses for 16 bit port size

Impact:
When 16 bit port size is used, accesses not aligned to 16 bit address boundary
will result in incorrect data

Workaround:
The workaround is to switch to GPCM mode for NOR Flash access.
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

For an IFC Erratum (A-003399) we will need to access IFC registers in
cpu_init_early_f() so expand the TLB covering CCSR to 1M.

Since we need a TLB to cover 1M we move to using TLB1 array for all the
early mappings so we can cover various sizes beyond 4k.
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>