- 11 6月, 2015 14 次提交
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由 Simon Glass 提交于
Allow SPL to be built with this option so that we can support device tree control. Disable the simple bus for now in SPL. It may be needed later. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
This is used when the full malloc() is not available. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
This feature should be deprecated for new boards, and significantly adds to SPL code size. Drop it. Instead, we can use stdout-path in the /chosen node. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
We plan to enable device tree in SPL by default. Before doing this, explicitly disable it for all boards. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
The 4KB padding doesn't seem necessary since we don't normally adjust the control device tree file within U-Boot. Also drop the memory table space. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
This option is used by some boards, so support it with driver model. This is really ugly - we should rewrite this driver once all users are moved to driver model. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
For 16-bit-per-pixel displays it is useful to support 8 bit-per-pixel images to reduce image size. Add support for this when drawing BMP images. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
We try to avoid typedefs and these ones are easy enough to remove. Before changing this header in the next patch, remove the typedefs. Signed-off-by: NSimon Glass <sjg@chromium.org> Suggested-by: NJoe Hershberger <joe.hershberger@gmail.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Simon Glass 提交于
Support this function so we can use Chrome OS verified boot with sandbox. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
This function is used before jumping to U-Boot, but in that case we don't always want to disable caches. Signed-off-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NVadim Bendebury <vbendeb@chromium.org>
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由 Simon Glass 提交于
For secure boot systems it is common to have a read-only U-Boot which starts the machine and jumps to a read-write U-Boot for actual booting the OS. This allows the read-write U-Boot to be upgraded without risk of permanently bricking the machine. In the event that the read-write U-Boot is corrupted, the read-only U-Boot can detect this with a checksum and boot into a recovery flow. To support this, add a way to detect when U-Boot is run from SPL as opposed to some other method, such as booted directly (no SPL) or started from another source (e.g. a primary U-Boot). This works by putting a special value in r0. For now we rely on board-specific code to actually check the register and set a flag. At some point this could be generalised, perhaps by using a spare register and passing a flag to _main and/or board_init_f(). This commit does not implement any feature, but merely provides the API for boards to implement. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Support this function with driver model also (CONFIG_DM_USB). Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Somehow this change was dropped in the various merges. I noticed when I came to turn off the non-driver-model support for Tegra. We need to make this change (and deal with any problems) before going further. Change-Id: Ib9389a0d41008014eb0df0df98c27be65bc79ce6 Signed-off-by: NSimon Glass <sjg@chromium.org> Acked-by: NMarek Vasut <marex@denx.de>
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由 Simon Glass 提交于
Add the legacy i2c_reg_read/write() functions to the compatibility layer so that they can be used when CONFIG_DM_I2C_COMPAT is defined. Signed-off-by: NSimon Glass <sjg@chromium.org> Acked-by: NHeiko Schocher <hs@denx.de>
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- 10 6月, 2015 26 次提交
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由 Bernhard Nortmann 提交于
Due to absence of CONFIG_SYS_64BIT_LBA, u-boot-sunxi currently has no support for the (GPT) partioning scheme of large disks > 2TB. While the AHCI driver seems to handle this nicely, the problem is that lbaint_t values get truncated to 32-bit. This patch sets CONFIG_SYS_64BIT_LBA from sunxi_common.h for all SoCs that support AHCI (CONFIG_SUNXI_AHCI). Signed-off-by: NBernhard Nortmann <bernhard.nortmann@web.de> Reviewed-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 Hans de Goede 提交于
This fixes ethernet no longer working on boards which use a gpio to enable the phy. Signed-off-by: NHans de Goede <hdegoede@redhat.com> Acked-by: NIan Campbell <ijc@hellion.org.uk>
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由 Andreas Bießmann 提交于
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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由 Andreas Bießmann 提交于
I have this board at work, so I can trun tests on it. Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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由 Andreas Bießmann 提交于
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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由 Andreas Bießmann 提交于
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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由 Andreas Bießmann 提交于
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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由 Andreas Bießmann 提交于
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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由 Andreas Bießmann 提交于
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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由 Simon Glass 提交于
We need to match the device tree in the FIT with the U-Boot model so we can automatically select the right device tree. Also adjust the load address so that the device tree is not in the way when a zImage kernel tries to extract itself. Signed-off-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Simon Glass 提交于
With the rename the MAINTAINER file was not updated. Fix it and the 'Chrombook' typo in Kconfig. Signed-off-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Simon Glass 提交于
Bring these in if they are provided by the board. Signed-off-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Simon Glass 提交于
We need to turn on all audio-related clocks for the Chrome OS kernel to boot. Otherwise it will hang when trying to enable audio. Also for Linux set up graphics driver video protection. Signed-off-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Simon Glass 提交于
Add a hook to allows boards to add their own init to board_init(). Signed-off-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Simon Glass 提交于
Use the correct function for clock init. Signed-off-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Simon Glass 提交于
When setting up large environment variables we can exceed 16 arguemnts. Increase this to avoid problems. Signed-off-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Simon Glass 提交于
There are some missing entries in the tables. Add them. Signed-off-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Simon Glass 提交于
This is required in order to avoid instability when running from caches after the kernel starts. Signed-off-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Simon Glass 提交于
A harmless but confusing warning is displayed when looking up the DisplayPort PLL. Correct this. Signed-off-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Simon Glass 提交于
Add a simple function to enable external clocks. Signed-off-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Simon Glass 提交于
Use the oscillator as the source clock when we cannot achieve a low-enough speed with the peripheral clock. This happens when we request 3MHz on a SPI clock, for example. Signed-off-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Simon Glass 提交于
Enable the EC and keyboard, using the SPI bus. The EC driver requires a particular format and a deactivation delay. Also U-Boot does not support interrupts. For now, adjust the device tree to comply. At some point we should tidy this up to support interrupts and make tegra and exynos use the same setup. Signed-off-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Simon Glass 提交于
At present the driver does not properly honour the requested SPI CS deactivation delay since the SPI bus is changed in the claim_bus() method. Everything the claim_bus() method does can be done when the device is probed (setting the speed and mode) and at the start of a new transfer (where the fifo_status is already cleared). So drop this method. Also, until the delay is complete, we should not touch the bus, so make sure that spi_cs_activate() is called before other things are done in the xfer() method. Signed-off-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Simon Glass 提交于
This requires a change to stdin to include the 'cros-ec-keyb' input device. Put this in the common file, enabled by the relevant CONFIG. Signed-off-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NTom Warren <twarren@nvidia.com>
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