The cfi-flash driver uses an open-coded version of the generic
algorithm to decode and translate multiple frames of a "reg" property.

This starts off the wrong foot by using the address-cells and size-cells
properties of *this* very node, and not of the parent. This somewhat
happened to work back when we were using a wrong default size of 2,
but broke about a year ago with commit 0ba41ce1 ("libfdt: return
correct value if #size-cells property is not present").

Instead of fixing the reinvented wheel, just use the generic function
that does all of this properly.

This fixes U-Boot on QEMU (-arm64), which was crashing due to decoding
a wrong flash base address:
DRAM:  1 GiB
Flash: "Synchronous Abort" handler, esr 0x96000044
elr: 00000000000211dc lr : 00000000000211b0 (reloc)
elr: 000000007ff5e1dc lr : 000000007ff5e1b0
x0 : 00000000000000f0 x1 : 000000007ff5e1d8
x2 : 000000007edfbc48 x3 : 0000000000000000
x4 : 0000000000000000 x5 : 00000000000000f0
x6 : 000000007edfbc2c x7 : 0000000000000000
x8 : 000000007ffd8d70 x9 : 000000000000000c
x10: 0400000000000003 x11: 0000000000000055
     ^^^^^^^^^^^^^^^^
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
Reviewed-by: NStefan Roese <sr@denx.de>

When possible use DMA for reading from CFI flash, this provides upto 5x
improvement in read performance with high speed CFI compliant flashes
like HyperFlash.

Code will gracefully fallback to CPU copy when DMA is unavailable.
Signed-off-by: NVignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: NStefan Roese <sr@denx.de>

Caller would need gracefully handle failures of dma_get_device(),
therefore reduce pr_err() to pr_debug() when DMA device is not found.
Signed-off-by: NVignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: NStefan Roese <sr@denx.de>

This patch adds the glue layer for the MIPS Octeon SoCs. It's ported
mainly from the Linux code.
Signed-off-by: NStefan Roese <sr@denx.de>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>

Octeon uses mapped addresses for virtual and physical memory. It's not
that easy to calculate the resulting addresses here. So let's remove
this BUG_ON() completely, as it's not really helpful.

Please also note, that BUG_ON() is not recommended any more in the Linux
kernel.
Signed-off-by: NStefan Roese <sr@denx.de>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>

On MIPS platforms, mapping of the base address is needed. This patch
switches from dev_get_addr() to dev_remap_addr() to get the mapped base
address of the xHCI controller.
Signed-off-by: NStefan Roese <sr@denx.de>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>

This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot
repository. It currently supports DDR4 on Octeon 3. It can be later
extended to support also DDR3 and Octeon 2 platforms.

Part 3 includes the DIMM SPD handling code and the Kconfig / Makefile
integration.
Signed-off-by: NAaron Williams <awilliams@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot
repository. It currently supports DDR4 on Octeon 3. It can be later
extended to support also DDR3 and Octeon 2 platforms.

Part 2 includes the very complex Octeon 3 DDR4 configuration
Signed-off-by: NAaron Williams <awilliams@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot
repository. It currently supports DDR4 on Octeon 3. It can be later
extended to support also DDR3 and Octeon 2 platforms.

Part 1 adds the base U-Boot RAM driver, which will be instantiated by
the DT based probing.
Signed-off-by: NAaron Williams <awilliams@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

The cell_count argument is required when cells_name is NULL.

This patch adds this parameter in live tree API
- of_count_phandle_with_args
- ofnode_count_phandle_with_args
- dev_count_phandle_with_args

This parameter solves issue when these API is used to count
the number of element of a cell without cell name. This parameter
allow to force the size cell.

For example:
  count = dev_count_phandle_with_args(dev, "array", NULL, 3);
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

This adds the driver for the PWM controller found in the Amlogic SoCs.

This PWM is only a set of Gates, Dividers and Counters:
PWM output is achieved by calculating a clock that permits calculating
two periods (low and high). The counter then has to be set to switch after
N cycles for the first half period.
The hardware has no "polarity" setting. This driver reverses the period
cycles (the low length is inverted with the high length) for
PWM_POLARITY_INVERSED.

Disabling the PWM stops the output immediately (without waiting for the
current period to complete first).
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>

Add the missing GPIOA_18 from the missing EE gpio list.
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>

The AXG pmx driver gpio request offset needs the pin base to have the
correct pin number.
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Reviewed-by: NMark Kettenis <kettenis@openbsd.org>

Enable build of meson-gxl-usb PHY for the AXG architecture aswell.
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>

The registers which are managed by the meson-gxl-usb3 PHY driver are
actually "USB control" registers (which are "glue" registers which
manage OTG detection and routing of the OTG capable port between the
DWC2 peripheral-only controller and the DWC3 host-only controller).

Drop the meson-gxl-usb3 PHY driver now that the dwc3-meson-gxl-usb
driver supports the USB control registers on GXL and GXM SoCs (these
were previously managed by the meson-gxl-usb3 PHY driver).
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>

The USB support was initialy done with a set of PHYs and dwc3-of-simple
because the architecture of the USB complex was not understood correctly
at the time (and proper documentation was missing...).

But with the G12A family, the USB complex was correctly understood and
implemented correctly.

This adds a proper driver for the glue, based on the G12A one, but with
enough changes to require a different driver in U-Boot.
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>

Add basic CPU driver use to retrieve information about CPU itself.
Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>

Currently, the return value of dev_read_u32_default is stored in an u32,
causing the subsequent "if (function < 0)" to always be false:

u32 function;
...
function = dev_read_u32_default(config, "brcm,function", -1);
if (function < 0) {
        debug("Failed reading function for pinconfig %s (%d)\n",
                      config->name, function);
        return -EINVAL;
}

Make "function" variable an int to fix this.

Cc: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: NOvidiu Panait <ovidiu.panait@windriver.com>
Signed-off-by: NMatthias Brugger <mbrugger@suse.com>

Factor out reading IP base address to ofdata_to_platdata function, which
is designed for this purpose. Also, drop the dev->priv NULL check, since
this is already done by the dm core when allocating space using
priv_auto_alloc_size feature. (in drivers/core/device.c ->
device_ofdata_to_platdata).

Cc: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: NOvidiu Panait <ovidiu.panait@windriver.com>
Signed-off-by: NMatthias Brugger <mbrugger@suse.com>

Remove CONFIG_IS_ENABLED(OF_CONTROL) check from DM_FLAG_PRE_RELOC, since
this driver only supports OF_CONTROL.

drivers/pinctrl/broadcom/Kconfig:
config PINCTRL_BCM283X
    depends on ARCH_BCM283X && PINCTRL_FULL && OF_CONTROL

Cc: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: NOvidiu Panait <ovidiu.panait@windriver.com>
Signed-off-by: NMatthias Brugger <mbrugger@suse.com>

Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the
driver can support live DT.
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: NPatrice Chotard <patrice.chotard@st.com>

Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the
driver can support live DT.
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NYannick Fertré <yannick.fertre@st.com>

Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the
driver can support live DT.
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: NYannick Fertré <yannick.fertre@st.com>
Reviewed-by: NPatrice Chotard <patrice.chotard@st.com>

Cosmetics: Add header with SPDX licence
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: NPatrice Chotard <patrice.chotard@st.com>

Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the
driver can support live DT.
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: NPatrice Chotard <patrice.chotard@st.com>

Add test on the size of ofnode_phandle_args result to avoid access
to uninitialized elements in args[] field.

This patch avoids the issue when gpio-ranges cell size is not 3 as
expected, for example:
	gpio-ranges = <&pinctrl 0>;
instead of
	gpio-ranges = <&pinctrl 0 112 16>;
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: NPatrice Chotard <patrice.chotard@st.com>

Move the variables definition at the beggining of the function
gpio_stm32_probe().
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: NPatrice Chotard <patrice.chotard@st.com>

Upon further discussion on the mailing list, we should not get in the
situation where the generic code path to set ethaddr/etc correctly does
not work.  Revert this until someone can further debug the smc911x
driver regarding this issue.

This reverts commit 387cbf09.
Signed-off-by: NTom Rini <trini@konsulko.com>

The R8A774A1 is compatible with the generic rcar-gen3-xhci controller.
This patch adds the compatibility flag, to support the xHCI controller.
Signed-off-by: NLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: NBiju Das <biju.das.jz@bp.renesas.com>

Use readx_poll_sleep_timeout() to poll the register status
Signed-off-by: NChunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Use macros with parameter to fill ep_info2, then some macros
for MASK and SHIFT can be removed
Signed-off-by: NChunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Use TRB_TX_TYPE() instead of (TRB_DATA_OUT/IN << TRB_TX_TYPE_SHIFT)
Signed-off-by: NChunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

For normal TRB fields:
use TRB_LEN(x) instead of ((x) & TRB_LEN_MASK);
and use TRB_INTR_TARGET(x) instead of
(((x) & TRB_INTR_TARGET_MASK) << TRB_INTR_TARGET_SHIFT)
Signed-off-by: NChunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Use TRB_TYPE(p) instead of ((p) << TRB_TYPE_SHIFT)
Signed-off-by: NChunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Use HCS_MAX_PORTS(p) instead of
((p & HCS_MAX_PORTS_MASK) >> HCS_MAX_PORTS_SHIFT)
Signed-off-by: NChunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

There some vendor quirks for MTK xHCI 0.96 host controller:
1. It defines some extra SW scheduling parameters for HW
   to minimize the scheduling effort for synchronous and
   interrupt endpoints. The parameters are put into reserved
   DWs of slot context and endpoint context.
2. Its TDS in  Normal TRB defines a number of packets that
   remains to be transferred for a TD after processing all
   Max packets in all previous TRBs.
Signed-off-by: NChunfeng Yun <chunfeng.yun@mediatek.com>
Tested-by: NFrank Wunderlich <frank-w@public-files.de>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

xhci versions 1.0 and later report the untransferred data remaining in a
TD a bit differently than older hosts.

We used to have separate functions for these, and needed to check host
version before calling the right function.

Now Mediatek host has an additional quirk on how it uses the TD Size
field for remaining data. To prevent yet another function for calculating
remainder we instead want to make one quirk friendly unified function.

Porting from the Linux:
c840d6ce772d("xhci: create one unified function to calculate TRB TD remainder.")
124c39371114("xhci: use boolean to indicate last trb in td remainder calculation")
Signed-off-by: NChunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Add a member to save xHCI version, it's used some times.
Signed-off-by: NChunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

commit 7c8f821e ("i2c: rcar_i2c: Set the slave address from
rcar_i2c_xfer") blindly called rcar_i2c_set_addr() with read argument
always set to 1 during xfer which introduced read/write errors, whereas
earlier rcar_i2c_read_common() called rcar_i2c_set_addr() with read set to
1 and rcar_i2c_write_common() called rcar_i2c_set_addr() with read set 0.

Fixes: 7c8f821e ("i2c: rcar_i2c: Set the slave address from rcar_i2c_xfer")
Signed-off-by: NLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the
driver can support live DT.
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>