1. 04 6月, 2021 3 次提交
    • P
      arm: a37xx: pci: Fix DT compatible string to Linux' DT compatible · a544d65f
      Pali Rohár 提交于
      Change DT compatible string for A3700 PCIe from 'marvell,armada-37xx-pcie'
      to 'marvell,armada-3700-pcie' to make U-Boot A3700 PCIe DT node compatible
      with Linux' DT node.
      Signed-off-by: NPali Rohár <pali@kernel.org>
      Reviewed-by: NMarek Behún <marek.behun@nic.cz>
      Reviewed-by: NStefan Roese <sr@denx.de>
      a544d65f
    • P
      arm: a37xx: pci: Disable bus mastering when unloading driver · 7b85aefd
      Pali Rohár 提交于
      Disable Root Bridge I/O space, memory space and bus mastering in Aardvark's
      remove method, which is called before booting Linux kernel.
      
      This ensures that PCIe device which was initialized and used by U-Boot
      cannot do new DMA transfers until Linux initializes PCI subsystem and loads
      appropriate drivers for the device.
      
      During initialization of PCI subsystem Linux in fact disables this bus
      mastering on Root Bridge (and later enables it when driver is loaded and
      configured), but there is a possibility of a small window after U-Boot
      boots Linux when bus mastering is enabled, which is not correct.
      Signed-off-by: NPali Rohár <pali@kernel.org>
      Reviewed-by: NMarek Behún <marek.behun@nic.cz>
      Reviewed-by: NStefan Roese <sr@denx.de>
      7b85aefd
    • P
      arm: a37xx: pci: Don't put link into LTSSM Recovery state during probe · 127dbec3
      Pali Rohár 提交于
      During our debugging of the Aardvark driver in Linux we have discovered
      that the PCIE_CORE_LINK_CTRL_STAT_REG register in fact controls standard
      PCIe Link Control Register for PCIe Root Bridge. This led us to discover
      that the name of the PCIE_CORE_LINK_TRAINING macro and the corresponding
      comment by this macro's usage is misleading; this bit in fact controls
      Retrain Link, which, according to PCIe base spec is defined as:
      
        A write of 1b to this bit initiates Link retraining by directing the
        Physical Layer LTSSM to the Recovery state. If the LTSSM is already in
        Recovery or Configuration, re-entering Recovery is permitted but not
        required.
      
      Entering Recovery state is normally done from LTSSM L0, L0s and L1 states.
      But since the pci-aardvark.c driver enables Link Training just a few lines
      above, the controller is not in L0 ready state yet. So setting aardvark bit
      PCIE_CORE_LINK_TRAINING does not actually enter Recovery state at this
      place.
      
      Moreover, trying to enter LTSSM Recovery state without other configuration
      is causing issues for some cards (e.g. Atheros AR9xxx and QCA9xxx). Since
      Recovery state is not entered, these issues are not triggered.
      
      Remove code which tries to enter LTSSM Recovery state completely.
      Signed-off-by: NPali Rohár <pali@kernel.org>
      Reviewed-by: NMarek Behún <marek.behun@nic.cz>
      Reviewed-by: NStefan Roese <sr@denx.de>
      127dbec3
  2. 02 6月, 2021 1 次提交
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  6. 27 5月, 2021 10 次提交