The Mele A1000G-quad and the Mele M9 have the same PCB, sofar we've been
using the same defconfig (and dts on the kernel side) for both models.
Unfortunately this does not work for the otg controller, on the M9 this
is routed to a micro-usb connector on the outside, while as on the
A1000G-quad it is connected to an usb to sata bridge.

This commit adds a new defconfig for the Mele-A1000G-quad to allow using
different otg controller settings on the 2 boards.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

Before this commit the code for determining the disconnect threshold was
checking for sun4i or sun6i assuming that those where the exception and
that newer SoCs use a disconnect threshold of 2 like sun7i does.

But it turns out that newer SoCs actually use a disconnect threshold of 3
and sun5i and sun7i are the exceptions, so check for those instead.

Here are the settings from the various Allwinner SDK sources:
 sun4i-a10: USBC_Phy_Write(usbc_no, 0x2a, 3, 2);
 sun5i-a13: USBC_Phy_Write(usbc_no, 0x2a, 2, 2);
 sun6i-a31: USBC_Phy_Write(usbc_no, 0x2a, 3, 2);
 sun7i-a20: USBC_Phy_Write(usbc_no, 0x2a, 2, 2);
 sun8i-a23: USBC_Phy_Write(usbc_no, 0x2a, 3, 2);
 sun8i-h3:  USBC_Phy_Write(usbc_no, 0x2a, 3, 2);
 sun9i-a80: USBC_Phy_Write(usbc_no, 0x2a, 3, 2);

Note this commit makes no functional changes for sun4i - sun7i, and
changes the disconnect threshold for sun8i to match what Allwinner uses.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

This updates r8a7794 QoS to revision 0.31 for ES1 and revision 0.321 for ES2.
Signed-off-by: NKouei Abe <kouei.abe.cp@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

This updates r8a7793 QoS to revision 0.311.
Signed-off-by: NKouei Abe <kouei.abe.cp@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

This updates r8a7791 QoS to revision 0.411.
Signed-off-by: NKouei Abe <kouei.abe.cp@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

This updates r8a7790 QoS to revision 0.973.
This commit can changed from KConfig to fit contents of the QoS.
Signed-off-by: NKouei Abe <kouei.abe.cp@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

The chip select 1 of the NAND controller is available if you want to
use, although the pins are shared with UART port 2.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The register value should be 1, not 4.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

PH1-Pro5 includes a newer version of DDR PHY IP.  Some registers
have been added to the reserved areas.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

One disadvantage of commit a26cd049 (arch: Make board selection
choices optional) is that Kconfig could create such an insane
.config file that no board is selected.

As PH1-Pro4 is the main stream of UniPhier SoC family, rip off the
"optional" again in favor of PH1-Pro4 as the default SoC.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

This file is only built for SPL.  These ifdef conditionals are
unnecessary because UniPhier platform now supports UART on SPL.
Show appropriate messages on error.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Cache coherency for SMP is cared by Linux.  In U-Boot, the secondary
CPU(s) are just sleeping.  Nothing in memory is shared with the
primary CPU.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

For the same reason as commit d0c47b3e (serial: UniPhier: use
32 bit register access), use "str" instead of "strb" for the LCR
register setting.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The business for UniPhier Soc family has been transferred from
Panasonic Corporation to Socionext Inc.

Update the SoC select menu in Kconfig.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

In the Linux coding style, it is recommended to include <linux/io.h>
rather than <asm/io.h>.  Follow this trend.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

sun8i can share the PSCI backend with sun6i. Only difference
is sun8i does not have CPU power clamp controls.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>

This adds PSCI support for sun6i. So far it only supports
the PWR_ON method.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>

The PSCI code only works for sun7i. Rename it with _sun7i suffix,
and build only if building for sun7i.

This paves the way for adding PSCI support for other platforms.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>

The PSCI CPU_ON code accesses quite a few registers. Document
their names to make it easier to cross reference.

Also explain "lock cpu" and "unlock cpu" as enabling/disabling
debug access.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>

This commit adds support to the sunxi SPL to load u-boot from the internal
NAND. Note this only adds support to access the boot partitions to load
u-boot, full NAND support to load the kernel, etc. from the nand data
partition will come later.
Signed-off-by: NRoy Spliet <r.spliet@ultimaker.com>
Reviewed-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>

Make sure definitions for NAND clock and DMA gate bits are the same
across boards.
Signed-off-by: NRoy Spliet <r.spliet@ultimaker.com>
Reviewed-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>

Signed-off-by: NRoy Spliet <r.spliet@ultimaker.com>
Reviewed-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>

Add initial sun9i (A80) support, only uart + mmc are supported for now.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

The latest versions of the fel tool support loading normal u-boot builds
directly, and this is now the preferred way to use the fel boot method.

This commit removes support for the old deprecated standalone fel builds.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

Unlike the A31 and the A23 the A33 actually has a SID inside the SoC again,
but sid[3] is 0 (at least on some SoCs), so it is better to use the axp221
sid.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

Add ARMv7M STM32F1 support including clocks, timer, gpio, and flash.
Signed-off-by: NMatt Porter <mporter@konsulko.com>

On ARM v7M, the processor will return to ARM mode when executing
a blx instruction with bit 0 of the address == 0. Always set it
to 1 to stay in thumb mode.
Signed-off-by: NMatt Porter <mporter@konsulko.com>

Switch to generic timer implementation from lib/time.c .
This also fixes a signed overflow which was in __udelay()
implementation.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Tyler Baker <tyler.baker@linaro.org>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>

Reorder the timer.h file so it can be included from board config file.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Tyler Baker <tyler.baker@linaro.org>

Trivially fix the include check in wdog.h.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Tyler Baker <tyler.baker@linaro.org>

add support for imx6dl based aristainetos2 board

U-Boot 2015.04-rc5-00066-g60f6ed4 (Apr 10 2015 - 08:46:27)

CPU:   Freescale i.MX6DL rev1.1 at 792 MHz
Reset cause: WDOG
Board: aristaitenos2
       Watchdog enabled
I2C:   ready
DRAM:  1 GiB
NAND:  1024 MiB
MMC:   FSL_SDHC: 0
SF: Detected N25Q128A with page size 256 Bytes, erase size 64 KiB, total 16 MiB
Display: lg4573 (480x800)
In:    serial
Out:   serial
Err:   serial
Net:   FEC [PRIME]
Hit any key to stop autoboot:  0
=>
Signed-off-by: NHeiko Schocher <hs@denx.de>

rework and unify i2c address names for different SoCs, which
use the mxc_i2c driver.
Signed-off-by: NHeiko Schocher <hs@denx.de>

add I2C4 modul for MX6DL based boards.
Signed-off-by: NHeiko Schocher <hs@denx.de>

We should not hardcode MXS_DMA_ALIGNMENT to 32, since we can not guarantee
that socs' cache line size is 32 bytes.
If on chips whose cache line size is 64 bytes, error occurs:
"
NAND:  ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0
ERROR: v7_dcache_inval_range - stop address is not aligned - 0xbdf1f4a0
ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0
"
Align MXS_DMA_ALIGNMENT with ARCH_DMA_MINALIGN whose value is same to
CONFIG_SYS_CACHELINE_SIZE if CONFIG_SYS_CACHELINE_SIZE defined.
Signed-off-by: NPeng Fan <Peng.Fan@freescale.com>
Acked-by: NMarek Vasut <marex@denx.de>

Due to licensing issues, the files ps7_init.c/h are not able to be
distributed with U-Boot source code.  Recent Xilinx tools also
provide the GPL variants (ps7_init_gpl.c/h), compatible with U-Boot
license.

Prior to this commit, we had to copy ps7_init files into
board/xilinx/zynq/ before the compile.

To be more user-friendly, let's include ps7_init_gpl.c/h for
Zedboard, MicroZed, ZC702, ZC706.

These init code have been taken from the hwplatform_templates
directory of Xilinx SDK 2014.4.

You can still use customized ps7_init_gpl.c/h by enabling
CONFIG_ZYNQ_CUSTOM_INIT.  The recommended directory for storing them
is now board/xilinx/zynq/custom_hw_platform, but board/xilinx/zynq
is still supported for backward compatibility.  The latter emits
a warning message to prompt users to gradually switch to the new
directory.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: NSören Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Prior to this commit, ZC702 and ZC706 shared the same configuration
and were built as follows:

ZC702: make zynq_zc70x_defconfig && make
ZC706: make zynq_zc70x_defconfig && make DEVICE_TREE=zynq-zc706

This commit introduces separate configuration for them, which makes
the next commit much easier.

Going forward, the recommended build commands are:

ZC702: make zynq_zc702_defconfig && make
ZC706: make zynq_zc706_defconfig && make

Although the old work flow is still supported, CONFIG_TARGET_ZC70X
has been marked as deprecated.  If used, the warning message is
shown to prompt users to switch to the new scheme.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Don't use error-prone arch timer code and instead use system
timer implementation to simplify our code.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Currently we need to build one U-boot image for each of the wandboard
variants: quad, dual-lite and solo.

By switching to SPL we can support all these variants with a single binary,
which is very convenient.

Based on the work from Richard Hu.

Tested kernel booting on the three boards.
Signed-off-by: NRichard Hu <hakahu@gmail.com>
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Tested-by: NVagrant Cascadian <vagrant@aikidev.net>
Reviewed-by: NStefano Babic <sbabic@denx.de>

ccsr_ddr structure is already defined in fsl_immap.h. Remove
this duplicated define. Move fixed timing into ls1021atwr.h.
Signed-off-by: NYork Sun <yorksun@freescale.com>
CC: Alison Wang <alison.wang@freescale.com>
Acked-by: NAlison Wang <alison.wang@freescale.com>

We've never tested the lvds panel support on sun6i+ SoCs until now, and
unsurprisingly the lvds code needed some fixes to work on my ga10h A33
tablet with lvds panel. This makes the panel on that tablet actually work.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>