Use the new common code to load a ramdisk. The functionality should not
change.
Signed-off-by: NSimon Glass <sjg@chromium.org>

At present code to load an image from a FIT is duplicated in the three
places where it is needed (kernel, fdt, ramdisk).

The differences between these different code copies is fairly minor.
Create a new function in the fit code which can handle any of the
requirements of those cases.
Signed-off-by: NSimon Glass <sjg@chromium.org>

These are not actually used in mkimage itself, but the image code (which
is common with mkimage) does use them. To avoid #ifdefs in the image code
just for mkimage, define dummy version of these here. The compiler will
eliminate the dead code anyway.

A better way to handle this might be to split out more things from common.h
so that mkimage can include them. At present any file that mkimage uses
has to be very careful what headers it includes.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Loading a ramdisk, kernel or FDT goes through similar stages. Create
a block of IDs for each task, and define a consistent numbering within
the block. This will allow use of common code for image loading.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Define a simple debug condition at the top of the file, to avoid using
lots of #ifdefs later on.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NJoe Hershberger <joe.hershberger@ni.com>

Define a simple debug condition at the top of the file, to avoid using
lots of #ifdefs later on.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NJoe Hershberger <joe.hershberger@ni.com>

The headers are a bit out of order, so fix them.
Signed-off-by: NSimon Glass <sjg@chromium.org>

There are a few over-long lines and other checkpatch problems in this area
of the code. Prepare the ground for the next patch by tidying these up.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NJoe Hershberger <joe.hershberger@ni.com>

These functions are now available, so use them to avoid extra code here.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NJoe Hershberger <joe.hershberger@ni.com>

Move this code into its own function, since it clutters up main_loop().
Signed-off-by: NSimon Glass <sjg@chromium.org>

There are two implementations of abortboot(). Turn these into two separate
functions, and create a single abortboot() which calls either one or the
other.

Also it seems that nothing uses abortboot() outside main, so make it static.

At this point there is no further use of CONFIG_MENU in main.c.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NJoe Hershberger <joe.hershberger@ni.com>

This function should be declared in net.h.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NJoe Hershberger <joe.hershberger@ni.com>

This is not currently used, since autoboot is not enabled for this
board, but the string is missing a parameter. Add it.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Acked-by: NAndreas Bießmann <andreas.devel@googlemail.com>

This patch is essentially an update of u-boot MTD subsystem to
the state of Linux-3.7.1 with exclusion of some bits:

- the update is concentrated on NAND, no onenand or CFI/NOR/SPI
flashes interfaces are updated EXCEPT for API changes.

- new large NAND chips support is there, though some updates
have got in Linux-3.8.-rc1, (which will follow on top of this patch).

To produce this update I used tag v3.7.1 of linux-stable repository.

The update was made using application of relevant patches,
with changes relevant to U-Boot-only stuff sticked together
to keep bisectability. Then all changes were grouped together
to this patch.
Signed-off-by: NSergey Lapin <slapin@ossfans.org>
[scottwood@freescale.com: some eccstrength and build fixes]
Signed-off-by: NScott Wood <scottwood@freescale.com>

Replace all relocate_code routines from ARM start.S files
with a single instance in file arch/arm/lib/relocate.S.
For PXA, this requires moving the dcache unlocking code
from within relocate_code into c_runtime_cpu_setup.
Signed-off-by: NAlbert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Tested-by: NSimon Glass <sjg@chromium.org>

Signed-off-by: NAlbert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Tested-by: NSimon Glass <sjg@chromium.org>

Signed-off-by: NAlbert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Tested-by: NSimon Glass <sjg@chromium.org>

Signed-off-by: NAlbert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Tested-by: NSimon Glass <sjg@chromium.org>

Conflicts:
	common/cmd_fpga.c
	drivers/usb/host/ohci-at91.c

Then we can get rid of the #ifdef CONFIG_TEGRA guard in cpu_init_crit.
Signed-off-by: NAxel Lin <axel.lin@ingics.com>
Tested-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

cpu_init_crit() can be skipped, but the code is still enabled requiring a
platform to supply lowlevel_init().
Signed-off-by: NAxel Lin <axel.lin@ingics.com>
Tested-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Make U-Boot aware of the Tegra20 SKU 7, and treat it identically
to any other Tegra20.

My Whistler board has a SoC with this SKU.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Make U-Boot aware of the Tegra114 SKU 1, and treat it identically
to any other Tegra114.

This value is used on (at least some) Dalmore boards with a production
rather than engineering chip. Such boards are in the hands of some
partners who want to use upstream U-Boot.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Even when eventually building u-boot-dtb-tegra.bin, separately building
u-boot-nodtb-tegra.bin can be useful, since building it encapsulates the
SPL padding step. If you want to tweak u-boot.dtb and regenerate
u-boot-dtb-tegra.bin, it is then a simple cat operation.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

When adjusting peripheral clocks always use find_best_divider()
instead of clk_get_divider() even when a secondary divider is not
available.  In the case where is requested clock is too slow to be
derived from the parent clock this allows a best effort to get close
to the requested clock.

This comes up for commands like "sf" where the user can pass a clock
speed on the command line or "sspi" where the clock is hardcoded to
1MHz, but the Tegra114 SPI controller can't go that low.
Signed-off-by: NAllen Martin <amartin@nvidia.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Tegra builds use the common u-boot-spl.lds now.
Signed-off-by: NTom Warren <twarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

Did a 'strings u-boot-dtb-tegra.bin | less' and saw that both
board and board_name == beaver. Didn't test as I have no T30
Beaver board here.
Signed-off-by: NTom Warren <twarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>
Tested-by: NStephen Warren <swarren@nvidia.com>

dcbi instruction has been used to clear D-cache lock. However, the cache
lock is persistent for e6500 core. Use dcblc to clear the lock explicitly.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Boot ROM code creates TLB entries for 3.5G space before entering
the u-boot. Earlier we were deleting these entries after early
initialization of CPU. In recent past, code has been added
to invalidate all these entries before relocation of u-boot code.
So this code to delete TLB entries after CPU initialization
is no longer required.
Signed-off-by: NRuchika Gupta <ruchika.gupta@freescale.com>
Acked-by: NMatthew McClintock <msm@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Signed-off-by: NShaveta Leekha <shaveta@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Current driver of p5040 assumes 10G port follows 1G port DTSEC5 in
eth port enum structure, it will assign mdio mux depend on this assumption.
This is not true with Fman V3, which added more 1G ports after port DTSEC5
in eth port enum structure, then 10G ports on p5040 will have wrong mdio mux.
So we use dynamic index for 10G ports instead of hardcoded enum value
when doing mdio mux for 10G ports.
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

B4420 is a subset of B4860. Merge them in config_mpc85xx.h to simplify
the defines.
- Removed #define CONFIG_SYS_FSL_NUM_CLUSTERS as this is used nowhere.
- defined CONFIG_SYS_NUM_FM1_10GEC to 0 for B4420 as it does not have 10G.

Also move CONFIG_E6500 out of B4860QDSds.h into config_mpc85xx.h.
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

SPANSION recommend S25FL128S supersedes S25FL129P, and the two flash
memory have the same device ID and Memory architecture. So they can
use the same config parameters.
Signed-off-by: NXie Xiaobo <X.Xie@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

PC board has different serdes clock setting with PB board, it uses same
serdes frequency setting on bank2 as on bank1. PC board can be distingushed
from PB board by checking CPLD version, if running on PC board, then fix
the serdes reference clock frequency of bank2.
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Crossbar switches were wrongly programmed to
route the CPRI lanes to SFP as the connectivity table
was not correct.
Modified it correctly for SFPs connections.
Signed-off-by: NShaveta Leekha <shaveta@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

QSGMII card has different PHY address against previous SGMII card.
We check the type of card in slots and set correct PHY address to
avoid complainning "PHY reset timed out" during u-boot booting up.
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

SW7[4] is the new bit which controls the mapping of eMMC vs SDHC.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

- Added SERDES2 PRTCLs = 0x98, 0x9E
- Default Phy Addresses for Teranetics PHY on XAUI card
	The PHY addresses of Teranetics PHY on XAUI riser card are assigned
	based on the slot it is in. Switches SW4[2:4] and SW6[2:4] on
	AMC2PEX-2S On B4860QDS, AMC2PEX card decide the PHY addresses on slot1
        and slot2
- Configure MDIO for 10Gig Mac
Signed-off-by: NSuresh Gupta <suresh.gupta@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Debug trace buffers are memory mapped in DCSR space beyond 4M.
Signed-off-by: NStephen George <stephen.george@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>