Signed-off-by: NGong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

1.Use "qixis_reset sd" to boot from SD
2.Use "qixis_reset sd_qspi" to boot from SD with QSPI support
3.Use "qixis_reset qspi" to boot from QSPI flash

On some SoCs such as LS1021A and LS1043A, IFC and QSPI could be
pin-multiplexed. So the switches are different between SD boot with
IFC support and SD boot with QSPI support. The default booting from
SD is with IFC support.

Once QSPI is enabled(IFC disabled), only use I2C to access QIXIS.
Signed-off-by: NGong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

This patch also exposes the complete DDR region(s) to Linux.
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

During the receive data training, the DDRC may complete on a
non-optimal setting that could lead to data corruption or
initialization failure.

Workaround: before setting MEM_EN, set DEBUG_29 register with
specific value for different data rates.
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Use wildcard to clean arch subdirectories, as it is cleaner than
listing all the arch which builds dtb.
Signed-off-by: NThomas Chou <thomas@wytron.com.tw>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

GPIO, I2C, LCD and HDMI are now implemented. We have more than one PMIC.
There is an implementation to run the CPU at full speed although it does
not seem to make much difference.

Update the README to cover recent developments.
Signed-off-by: NSimon Glass <sjg@chromium.org>

This board includes an RK3288 SoC on a SOM. It can be mounted on a
base-board which provides a wide range of peripherals.

So far this is verified to boot to a prompt from a microSD card. The serial
console works as well as HDMI.

Thanks to Tom Cubie for sending me a board.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Add the required pre-relocation tags and SDRAM init information for U-Boot.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Bring in the current device tree files for rock2 from linux/next commit
719d6c1. Hopefully this is the latest one.
Signed-off-by: NSimon Glass <sjg@chromium.org>

This has been added and we have references to it in the rock2 board. Add
this node.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Enable HDMI output and a console on firefly.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Enable these devices using the VOPL video output device. We explicitly
disable VOPB in the device tree to avoid it taking over. Since this device
has an LCD display this comes up by default. If the display fails for some
reason then it will attempt to use HDMI. It is possible to force it to fail
(and thus fall back to HDMI) by puting 'return -EPERM' at the top of
rk_edp_probe(). For now there is no easy way to select between the two.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Add the 'time' and 'sf test' commands so that we can test SPI flash
performance.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Add a feature which speeds up the CPU to full speed in SPL to minimise
boot time. This is only supported for certain boards (at present only
jerry).
Signed-off-by: NSimon Glass <sjg@chromium.org>

Since the device tree does not specify the EDID pinctrl option for HDMI we
must set it manually. Fix the driver to handle this.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Fix a number of small errors which were found in reviewing the clock code.
Signed-off-by: NSimon Glass <sjg@chromium.org>

There is a minor error in the SDRAM timing. It does not seem to affect
anything so far. Fix it just in case.
Signed-off-by: NSimon Glass <sjg@chromium.org>

When the board does not use MMC SPL this code is a waste of space. Drop it.
Signed-off-by: NSimon Glass <sjg@chromium.org>

These work reasonable well, but there are a few errors:

- Brackets should be used to avoid unexpected side-effects
- When setting bits, the corresponding upper 16 bits should be set also
Signed-off-by: NSimon Glass <sjg@chromium.org>

This is a shortcut to obtaining a register address. Use it where possible, to
simplify the code.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Fix spaces in two comments in this file.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Now that we have a pretty good GPIO driver, enable the 'gpio' command on all
rockchip boards.
Signed-off-by: NSimon Glass <sjg@chromium.org>

This script has proved useful for parsing datasheets and creating register
shift/mask values for use in header files. Include it in case it is useful
for others.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Add a command that displays the PLLs and their current rate.
Signed-off-by: NSimon Glass <sjg@chromium.org>

At present the low-level init is skipped on rockchip. Among other things
this means that the instruction cache is left disabled. Fix this.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Some rockchip SoCs include video output (VOP). Add a driver to support this.
It can output via a display driver (UCLASS_DISPLAY) and currently HDMI and
eDP are supported.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Some Rockchip SoCs support embedded DisplayPort output. Add a display driver
for this so that these displays can be used on supported boards.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Some Rockchip SoCs support HDMI output. Add a display driver for this so
that these displays can be used on supported boards.

Unfortunately this driver is not fully functional. It cannot reliably read
EDID information over HDMI. This seems to be due to the clocks being
incorrect - the I2C bus speed appears to be up to 100x slower than the
clock settings indicate. The root cause may be in the clock logic.
Signed-off-by: NSimon Glass <sjg@chromium.org>

The displays need to use NPLL and also select some new peripheral clocks.
Add support for these to the clock driver.
Signed-off-by: NSimon Glass <sjg@chromium.org>

These should match the datasheet naming. Adjust them.
Signed-off-by: NSimon Glass <sjg@chromium.org>

The current DisplayPort uclass is too specific. The operations it provides
are shared with other types of output devices, such as HDMI and LVDS LCD
displays.

Generalise the uclass so that it can be used with these devices as well.
Adjust the uclass to handle the EDID reading and conversion to
display_timing internally.

Also update nyan-big which is affected by this.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Most panels are very simple - they just have a power supply and a backlight.
Add a driver which supports this and implements the enable_backlight()
method.
Signed-off-by: NSimon Glass <sjg@chromium.org>

LCD panels can usefully be modelled as their own uclass. They can be probed
(which powers them up ready for use). If they have a backlight, this can be
enabled.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Many backlights need to use a PWM to control the brightness. Add a driver
for this. It understands the standard device tree binding.
Signed-off-by: NSimon Glass <sjg@chromium.org>

LCD panels normally have a backlight which can be controlled to illuminate
the LCD contents. Add a uclass to support this. Initially it only has a
method to enable the backlight.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Add a simple driver which implements the standard PWM uclass interface.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Add a uclass that supports Pulse Width Modulation (PWM) devices. It
provides methods to enable/disable and configure the device.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Some video bridges will not have GPIOs to control reset, etc. Allow these
to be optional.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Allow the cache-flushing function of a video device to be controlled.
Signed-off-by: NSimon Glass <sjg@chromium.org>