- CONFIG_PHYLIB
- CONFIG_PHY_SMSC
- CONFIG_PHY_MICREL
- CONFIG_PHY_MICREL_KSZ9021
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>

Add kconfig entry for Micrel KSZ9021 PHY support.

Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>

nand defconfig is accidentally removed from below
commit, so recover the same.
"icorem6: Make SPL to pick suitable fdt"
(sha1: 15455a6b)
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>

- CONFIG_SYS_FSL_USDHC_NUM
- CONFIG_SYS_FSL_ESDHC_ADDR
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>

Don't build non DM_MMC code when DM_MMC defined so move
them into #ifndef CONFIG_DM_MMC

Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>

Fix unsigned compared against 0.
Signed-off-by: NPeng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>

Add SPDX license
Signed-off-by: NPeng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>

The maximum SD clock frequency in High Speed mode is 50 MHz. This change
makes it possible to get 48 MHz from the USB PLL (240 MHz / 5 / 1)
instead of the previous 33.25 MHz from the AHB clock (133 MHz / 2 / 2).
Signed-off-by: NBenoît Thébaudeau <benoit@wsystem.com>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>

Introduce the imx_set_perclk() function to make it possible to set the
PER clocks.
Signed-off-by: NBenoît Thébaudeau <benoit@wsystem.com>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>

imx_get_perclk() used the AHB clock as the clock source for all PER
clocks, but the USB PLL output can also be a PER clock source if the
corresponding PER CLK MUX bit is set in CCM.MCR.
Signed-off-by: NBenoît Thébaudeau <benoit@wsystem.com>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>

On i.MX, SYSCTL.SDCLKFS may be set to 0 in order to make the SD clock
frequency prescaler divide by 1 in SDR mode. In DDR mode, the prescaler
can divide by up to 512. Allow both of these settings.

The maximum SD clock frequency in High Speed mode is 50 MHz. On i.MX25,
this change makes it possible to get 48 MHz from the USB PLL
(240 MHz / 5 / 1) instead of only 40 MHz from the USB PLL
(240 MHz / 3 / 2) or 33.25 MHz from the AHB clock (133 MHz / 2 / 2).
Signed-off-by: NBenoît Thébaudeau <benoit@wsystem.com>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>

The config variable CONFIG_SPL_NAND_MXS is only set in
include/configs/imx6_spl.h but used nowhere.
Remove it.
Signed-off-by: NLothar Waßmann <LW@KARO-electronics.de>
Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>

There is no dedicated reset signal wired up for the MX6QDL thus if the
bootloader enables the link we need some special handling to get the core
back into a state where it is safe to touch it for configuration.

While there has been some special handling in the Linux kernel to do this,
it was removed in 4.11 thus we need to do it properly in the bootloader
and therefore without this if you enable PCI in the bootloader you will hang
while booting the 4.11 kernel.

This puts the PCIe controller back into a safe state for the kernel driver
before launching the kernel.
Signed-off-by: NTim Harvey <tharvey@gateworks.com>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>
Tested-by: NPeter Senna Tschudin <peter.senna@collabora.com>

After running 'saveenv' we can no longer boot.

Adjust CONFIG_ENV_OFFSET so that U-Boot binary and the environment
section do not overlap.
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>

Add the initial support for pico-imx7d board based on Wig Cheng's
source code.

Add support for eMMC, USB gadget, I2C, PMIC and Ethernet.

For more information about this board, please visit:
http://www.technexion.org/products/pico/pico-som/pico-imx7-emmcSigned-off-by: NVanessa Maegima <vanessa.maegima@nxp.com>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>

Adding documentation on the new config properties:
       'u-boot,mmc-env-offset' - overrides CONFIG_ENV_OFFSET
       'u-boot,mmc-env-offset-redundant'
                               - overrides CONFIG_ENV_OFFSET_REDUND
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>

This introduces the ability to override the environment offets from the
device tree by setting the following nodes in '/config':
	'u-boot,mmc-env-offset' - overrides CONFIG_ENV_OFFSET
	'u-boot,mmc-env-offset-redundant'
				- overrides CONFIG_ENV_OFFSET_REDUND

To keep with the previous logic, the CONFIG_* defines still need to
be available and the statically defined values become the defaults,
when the corresponding properties are not set in the device-tree.
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Currently while setting the vsel value for dcdc1 and dcdc2
the driver is wrongly masking the entire 8 bits in the process
clearing PFM (bit7) field as well. Hence describe an appropriate
mask for vsel field and modify only those bits in the vsel
mask.

Source: http://www.ti.com/lit/ds/symlink/tps65218.pdfSigned-off-by: NKeerthy <j-keerthy@ti.com>
Fixes: 86db550b ("power: Add support for the TPS65218 PMIC")
Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>

Number of blocks is a 9 bit field where 0 stands for a unlimited
number of blocks. Therefore the max number of blocks which can
be set is 511.
Signed-off-by: NHeiner Kallweit <hkallweit1@gmail.com>

Inside of
max77686_buck_volt2hex/max77686_buck_hex2volt/max77686_ldo_volt2hex we
check that the value we calculate is >= 0 however we declare 'hex' as
unsigned int making these always true.  Mark these as 'int' instead.  We
also move hex_max to int as they are constants that are 0x3f/0xff.
Given that the above functions are marked as returning an int, make the
variables we assign their return value to also be int to be able to
catch the error condition now.  Reported by clang-3.8.

Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NTom Rini <trini@konsulko.com>

In some places we check if part_config is set to MMCPART_NOAVAILABLE
(0xff).  With part_config being a char this is always false.  We should
be using a u8 to store this value instead, after a quick consultation
with the Linux Kernel.  Reported by clang-3.8.

Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NTom Rini <trini@konsulko.com>

Move FTMAC100 to where it should be, alphabetically in
drivers/net/Kconfig
Signed-off-by: NTom Rini <trini@konsulko.com>

Conflicts:
	drivers/net/Kconfig

This patch adjusts memory map for secure boot headers on LS2080AQDS
and LS2080ARDB platforms. Secure boot headers are placed on NOR
flash at offset 0x00600000.
Signed-off-by: NUdit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

This patch adjusts memory map for images on LS2080ARDB and
LS2080AQDS NOR flash as below

Image				Flash Offset
RCW+PBI				0x00000000
Boot firmware (U-Boot)		0x00100000
Boot firmware Environment	0x00300000
PPA firmware			0x00400000
PHY firmware			0x00980000
DPAA2 MC			0x00A00000
DPAA2 DPL			0x00D00000
DPAA2 DPC			0x00E00000
Kernel.itb			0x01000000
Signed-off-by: NSantan Kumar <santan.kumar@nxp.com>
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

This patch is to adjust the memory mapping for FLash/SD card on
LS1046AQDS and LS1046ARDB, such as FMAN firmware load address, U-Boot
start address on serial flash and environment address.
Signed-off-by: NAlison Wang <alison.wang@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

This patch is to adjust the memory mapping for FLash/SD card on
LS1043AQDS and LS1043ARDB, such as PPA firmware load address, FMAN
firmware load address, QE firmware load address, U-Boot start address
on serial flash and environment address.
Signed-off-by: NAlison Wang <alison.wang@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

This patch is to adjust the memory mapping for FLash/SD card on
LS1021AQDS and LS1021ATWR, such as U-Boot start address on serial
Flash, QE firmware load address and environment address.
Signed-off-by: NAlison Wang <alison.wang@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

LS2081ARDB board is similar to LS2080ARDB board with few differences
 It hosts LS2081A SoC
 Default boot source is QSPI-boot
 It does not have IFC interface
 RTC and QSPI flash device are different
 It provides QIXIS access via I2C
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: NSantan Kumar <santan.kumar@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and
is built on layerscape architecture. It is 40-pin derivative of
LS2084A (non-AIOP personality of LS2088A). So feature-wise it is
same as LS2084A. LS2041A is a 4-core personality of LS2081A.
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: NSantan Kumar <santan.kumar@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

QSPI-boot is supported on LS2088ARDB RevF board with LS2088A SoC.
LS2088ARDB RevF Board has limitation that QIXIS can not be accessed.
CONFIG_FSL_QIXIS is not enabled.
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: NSuresh Gupta <suresh.gupta@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Update QIXIS related code to be executed only if CONFIG_FSL_QIXIS
flag is enabled. In case QIXIS code is not enabled, use default
sysclk value as 100MHz per board documentation.
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Earlier when MC is loaded but DPL is not deployed results in FDT
fix-up code execution hangs. For this case now print message on
console and return success instead of return -ENODEV. This update
allows fdt fixup to continue execution.
Signed-off-by: NYogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: NPriyanka Jain <Priyanka.jain@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

This allows using PCIe NIC without enabling DPAA FMan.
Signed-off-by: NYork Sun <york.sun@nxp.com>
CC: Mingkai Hu <mingkai.hu@nxp.com>
Acked-by: NMingkai Hu <mingkai.hu@nxp.com>

This allows using PCIe NIC without enabling DPAA FMan.
Signed-off-by: NYork Sun <york.sun@nxp.com>
CC: Mingkai Hu <mingkai.hu@nxp.com>
Acked-by: NMingkai Hu <mingkai.hu@nxp.com>

LS1012AFRDM, LS1012ARDB, LS1012AQDS all have S25FS512S flash
of 64MB size.
Signed-off-by: NSuresh Gupta <suresh.gupta@nxp.com>

ls1012ardb, ls1046ardb, ls2080ardb have S25FS512S flash which does
not support Bank Address Register commands.
Signed-off-by: NSuresh Gupta <suresh.gupta@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

LS2080ARDB/LS2088ARDB RevF board has smart voltage translator
which needs to be programmed to enable high speed SD interface
by setting GPIO4_10 output to zero.
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: NSantan Kumar <santan.kumar@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>