get_ddr_freq() and get_bus_freq() used get_sys_info() each time they were
called.  However, get_sys_info() recalculates extraneous information when
called each time.  Have get_ddr_freq() and get_bus_freq() return memoized
values from global_data instead.
Signed-off-by: NJames Yang <James.Yang@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Show the DDR memory data rate in addition to the memory clock
frequency.  For DDR/DDR2 memories the memory data rate is 2x the
memory clock.
Signed-off-by: NJames Yang <James.Yang@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Speed up get_tbclk() by referencing pre-computed bus clock
frequency value from global data instead of sys_info_t.  Fix
rounding of result to nearest; previously it was rounding
upwards.
Signed-off-by: NJames Yang <James.Yang@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

FSL has taken to using SVR[16:23] as an SOC sub-version field.  This
is used to distinguish certain variants within an SOC family.  To
account for this, we add the SVR_SOC_VER() macro, and update the SVR_*
constants to reflect the larger value.  We also add SVR numbers for all
of the current variants.  Finally, to make things neater, rather than
use an enormous switch statement to print out the CPU type, we create
and array of SVR/name pairs (using a macro), and print out the CPU name
that matches the SVR SOC version.
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Signed-off-by: NAndy Fleming <afleming@freescale.com>

Added the cpu command that provides a generic mechanism to get status,
reset, and release secondary cores in multicore processors.

Added support for using the ePAPR defined spin-table mechanism on 85xx.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Added the cpu command that provides a generic mechanism to get status,
reset, and release secondary cores in multicore processors.

Added support for using the ePAPR defined spin-table mechanism on 85xx.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

When we go to 36-bit physical addresses we need to keep the concept of
the physical CCSRBAR address seperate from the virtual one.

For the majority of boards CFG_CCSBAR_PHYS == CFG_CCSRBAR
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Signed-off-by: NWolfgang Denk <wd@denx.de>

The default settings for RTC DS1337 keeps the OSC
output, 32,768 Hz, on. This add CFG_RTC_DS1337_NOOSC to
turn it off.
Signed-off-by: NJoakim Tjernlund <Joakim.Tjernlund@transmode.se>

Signed-off-by: NWolfgang Denk <wd@denx.de>

Signed-off-by: NWolfgang Denk <wd@denx.de>

Conflicts:

	common/cmd_bootm.c
	cpu/mpc8xx/cpu.c
Signed-off-by: NBartlomiej Sieka <tur@semihalf.com>

This patch changes the "usb storage" command to return success if it
finds a USB storage device, otherwise it returns error.
Signed-off-by: NMarkus Klotzbuecher <mk@denx.de>

Linux understands "host" (default), "peripheral" and "otg" (broken).
Though, U-Boot doesn't restrict dr_mode variable to these values (think
of renames in future).
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

RTL8211B sets link state register after autonegotiation complete,
so with bootdelay=0 RTL8211B will report lack of the link.

To fix this, we should wait for aneg to complete, even if the
link is currently down.
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

device_type = "soc" is being deprecated, newer device trees will use
"fsl,soc" and/or "fsl,immr" for the soc nodes.

This patch also adds clock-frequency property for soc nodes (the same
value as bus-frequency).
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>

With the original value of 1/2 clock cycle delay, the system ran relatively
stable except when we run benchmarks that are intensive users of memory.
When I run samba connected disk with a HDBENCH test, the system locks-up
or reboots sporadically.

Signed-off by: Joe D'Abbraccio <Joe.D'abbraccio@freescale.com>

The device trees for these boards describe PCI I/O as starting from
address zero from the device's perspective.

Placing I/O elsewhere may cause problems with certain PCI boards, and may
cause problems with Linux.
Signed-off-by: NScott Wood <scottwood@freescale.com>

At least on the "33MHz Pilot" board crystal is actually 33.3MHz.
This patch fixes "system time drifting" problem.
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>

This is needed to update /choosen/linux,stdout-path properly.
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>

Plus modify environment to use it and remove bootfile env variable,
it is internal and CONFIG_BOOTFILE is used for these purposes.
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>

Current DDR setup easily causes memory corruption, this patch fixes it.

Also fix TIMING_CFG0_MRS_CYC definition.
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>

This patch adds qe pario pins configuration for AD7843 ADC/Touchscreen
controller and FHCI (QE USB).
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>

Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>

This is needed for BCM PHYs to work on this board.
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>

This patch adds basic support for Broadcom BCM5481 PHY.

RXD-RXC delay quirk comes from MPC8360E-RDK BSP source, author is
Peter Barada <peterb@logicpd.com>.
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>

PHY drivers will use it to setup software delay between RXD and RXC
signals.
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>

Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>

This is primarily for the early console support.
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>

On the MPC8377ERDB: 2 SATA and 2 PCI-E.
On the MPC8378ERDB: 2 PCI-E
On the MPC8379ERDB: 4 SATA
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>

This patch adds few routines to configure serdes on 837x targets.
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>

..plus get rid of some #ifdefs in the .c files.
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>

Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>

Signed-off-by: NGerald Van Baren <vanbaren@cideas.com>
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

There's no on-board RTC on the MPC8323ERDB, but there is an EEPROM.
Signed-off-by: NMichael Barkowski <michael.barkowski@freescale.com>
Acked-by: NKim Phillips <kim.phillips@freescale.com>

The following changes are based on kernel UCC ethernet performance:

1.  Make the CSB bus pipeline depth as 4, and enable the repeat mode
2.  Optimize transactions between QE and CSB.  Added CFG_SPCR_OPT
    switch to enable this setting.

The following changes are based on the App Note AN3369 and
verified to improve memory latency using LMbench:

3.  CS0_CONFIG[AP_n_EN] is changed from 1 to 0
4.  CS0_CONFIG[ODT_WR_CONFIG] set to 1.  Was a reserved setting
    previously.
5.  TIMING_CFG_1[WRREC] is changed from 3clks to 2clks  (based on
    Twr=15ns, and this was already the setting in DDR_MODE)
6.  TIMING_CFG_1[PRETOACT] is changed from 3clks to 2clks. (based on
    Trp=15ns)
7.  TIMING_CFG_1[ACTTOPRE] is changed from 9clks to 6clks. (based on
    Tras=40ns)
8.  TIMING_CFG_1[ACTTORW] is changed from 3clks to 2clks. (based on
    Trcd=15ns)
9.  TIMING_CFG_1[REFREC] changed from 21 clks to 11clks.  (based on
    Trfc=75ns)
10. TIMING_CFG_2[FOUR_ACT] is changed from 10 clks to 7clks.  (based
    on Tfaw=50ns)
11. TIMING_CFG_2[ADD_LAT] and DDR_MODE[AL] changed from 0 to 1 (based
    on CL=3 and WL=2).
Signed-off-by: NMichael Barkowski <michael.barkowski@freescale.com>
Acked-by: NKim Phillips <kim.phillips@freescale.com>

Use available shift/mask macros to define DDR configuration.
Signed-off-by: NMichael Barkowski <michael.barkowski@freescale.com>
Acked-by: NKim Phillips <kim.phillips@freescale.com>

Update the MPC8349E-mITX, MPC8313E-RDB, and MPC837XE-RDB board files to upload
the Vitesse VSC7385 firmware.  Changed CONFIG_VSC7385 to CONFIG_VSC7385_ENET.
Cleaned up the board header files to make selecting the VSC7385 easier to
control.
Signed-off-by: NTimur Tabi <timur@freescale.com>
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>