1. 07 4月, 2010 9 次提交
  2. 01 4月, 2010 2 次提交
  3. 31 3月, 2010 6 次提交
  4. 30 3月, 2010 3 次提交
    • T
      mpc86xx: set the DDR BATs after calculating true DDR size · 9ff32d8c
      Timur Tabi 提交于
      After determining how much DDR is actually in the system, set DBAT0 and
      IBAT0 accordingly.  This ensures that the CPU won't attempt to access
      (via speculation) addresses outside of actual memory.
      
      On 86xx systems, DBAT0 and IBAT0 (the BATs for DDR) are initialized to 2GB
      and kept that way.  If the system has less than 2GB of memory (typical for
      an MPC8610 HPCD), the CPU may attempt to access this memory during
      speculation.  The zlib code is notorious for generating such memory reads,
      and indeed on the MPC8610, uncompressing the Linux kernel causes a machine
      check (without this patch).
      
      Currently we are limited to power of two sized DDR since we only use a
      single bat.  If a non-power of two size is used that is less than
      CONFIG_MAX_MEM_MAPPED u-boot will crash.
      Signed-off-by: NTimur Tabi <timur@freescale.com>
      Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      9ff32d8c
    • K
      85xx: Fix enabling of L1 cache parity on secondary cores · 33f57bd5
      Kumar Gala 提交于
      Use the same code between primary and secondary cores to init the
      L1 cache.  We were not enabling cache parity on the secondary cores.
      
      Also, reworked the L1 cache init code to match the e500mc L2 init code
      that first invalidates the cache and locks.  Than enables the cache and
      makes sure its enabled before continuing.
      Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      33f57bd5
    • S
      ppc4xx: Fix problem with I2C bus >= 1 initialization · 1a332da6
      Stefan Roese 提交于
      This patch fixes a problem introduced with patch eb5eb2b0
      [ppc4xx: Cleanup PPC4xx I2C infrastructure]. We need to assign the I2C
      base address to the "i2c" pointer inside of the controller loop.
      Otherwise controller 0 is initialized multiple times instead of
      initializing each I2C controller sequentially.
      
      Tested on Katmai.
      Signed-off-by: NStefan Roese <sr@denx.de>
      Acked-by: NHeiko Schocher <hs@denx.de>
      1a332da6
  5. 29 3月, 2010 8 次提交
  6. 28 3月, 2010 7 次提交
  7. 26 3月, 2010 1 次提交
    • T
      cfi flash: add status polling method for amd flash · e5720823
      Thomas Chou 提交于
      This patch adds status polling method to offer an alternative to
      data toggle method for amd flash chips.
      
      This patch is needed for nios2 cfi flash interface, where the bus
      controller performs 4 bytes read cycles for a single byte read
      instruction. The data toggle method can not detect chip busy
      status correctly. So we have to poll DQ7, which will be inverted
      when the chip is busy.
      
      This feature is enabled with the config def,
      CONFIG_SYS_CFI_FLASH_STATUS_POLL
      Signed-off-by: NThomas Chou <thomas@wytron.com.tw>
      Signed-off-by: NStefan Roese <sr@denx.de>
      e5720823
  8. 25 3月, 2010 4 次提交