- 15 11月, 2010 21 次提交
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由 Peter Tyser 提交于
Move the printing of PCI device information to before the PCI device is configured. This prevents the case where recursive scanning results in the deepest devices being printed first. This change also makes PCI lockups during enumeration easier to diagnose since the device that is being configured is printed out prior to configuration. Previously, it was not possible to determine which device caused the PCI lockup. Original example: PCIE1: connected as Root Complex 04:01.0 - 8086:1010 - Network controller 04:01.1 - 8086:1010 - Network controller 03:00.0 - 10b5:8112 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 08:00.0 - 1957:0040 - Processor 07:00.0 - 10b5:8518 - Bridge device 09:00.0 - 10b5:8112 - Bridge device 07:01.0 - 10b5:8518 - Bridge device 07:02.0 - 10b5:8518 - Bridge device 06:00.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device 01:00.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 0b Updated example: PCIE1: connected as Root Complex 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 03:00.0 - 10b5:8112 - Bridge device 04:01.0 - 8086:1010 - Network controller 04:01.1 - 8086:1010 - Network controller 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device 06:00.0 - 10b5:8518 - Bridge device 07:00.0 - 10b5:8518 - Bridge device 08:00.0 - 1957:0040 - Processor 07:01.0 - 10b5:8518 - Bridge device 09:00.0 - 10b5:8112 - Bridge device 07:02.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 0b Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
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由 Peter Tyser 提交于
This change does the following: - Removes the printing of the PCI interrupt line value. This is normally set to 0 by U-Boot on bootup and is rarely used during everyday operation. - Prints out the PCI function number of a device. Previously a device with multiple functions would be printed identically 2 times, which is generally confusing. For example, on an Intel 2 port gigabit Ethernet card the following was displayed: ... 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 ... - Prints a text description of each device's PCI class instead of the raw PCI class code. The textual description makes it much easier to determine what devices are installed on a PCI bus. - Changes the general formatting of the PCI device output. Previous output: PCIE1: connected as Root Complex 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d Updated output: PCIE1: connected as Root Complex 04:01.0 - 8086:1010 - Network controller 04:01.1 - 8086:1010 - Network controller 03:00.0 - 10b5:8112 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 08:00.0 - 1957:0040 - Processor 07:00.0 - 10b5:8518 - Bridge device 09:00.0 - 10b5:8112 - Bridge device 07:01.0 - 10b5:8518 - Bridge device 07:02.0 - 10b5:8518 - Bridge device 06:00.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device 01:00.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d:00.0 - 1957:0040 - Processor PCIE2: Bus 0c - 0d Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
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由 Peter Tyser 提交于
The "Scanning PCI bus X" message doesn't provide any real useful information, so remove it. Original output: PCIE1: connected as Root Complex Scanning PCI bus 01 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex Scanning PCI bus 0d 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d Updated output: PCIE1: connected as Root Complex 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d Signed-off-by: NPeter Tyser <ptyser@xes-inc.com> CC: galak@kernel.crashing.org
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由 Peter Tyser 提交于
Previously some mpc85xx boards printed indented messages such as the following on bootup: printf(" eTSEC4 is in sgmii mode.\n"); printf(" Serdes2 disalbed\n"); The bootup appearance looks cleaner if the indentation is removed which aligns these messages with other bootup output. Signed-off-by: NPeter Tyser <ptyser@xes-inc.com> CC: galak@kernel.crashing.org
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由 Peter Tyser 提交于
Previously boards used a variety of indentations, newline styles, and colon styles for the PCI information that is printed on bootup. This patch unifies the style to look like: ... NAND: 1024 MiB PCIE1: connected as Root Complex Scanning PCI bus 01 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex Scanning PCI bus 0d 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d In: serial ... Signed-off-by: NPeter Tyser <ptyser@xes-inc.com> CC: wd@denx.de CC: sr@denx.de CC: galak@kernel.crashing.org
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由 Peter Tyser 提交于
Previously fsl_pci_init_port() always assumed that a port was a PCIe port and would incorrectly print messages for a PCI port such as the following on bootup: PCI1: 32 bit, 33 MHz, sync, host, arbiter Scanning PCI bus 00 PCIE1 on bus 00 - 00 This change corrects the output of fsl_pci_init_port(): PCI1: 32 bit, 33 MHz, sync, host, arbiter Scanning PCI bus 00 PCI1 on bus 00 - 00 Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
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由 Jason Liu 提交于
Can't get IP address with dhcp due to the dhcp server not allow the empty param list request under some network env This patch is based on Gray Remlin's initial patch. Signed-off-by: NJason Liu <r64343@freescale.com> Signed-off-by: NGray Remlin <g_remlin@rocketmail.com>
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由 Lei Wen 提交于
hexport would complain implicit declaration, if we don't add the include file. env_mmc.c: In function 'saveenv': env_mmc.c:109: warning: implicit declaration of function 'hexport' Signed-off-by: NLei Wen <leiwen@marvell.com>
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由 Daniel Hobi 提交于
This patch makes tools/env/Makefile more similar to tools/imls: - define HOSTSRCS and HOSTCPPFLAGS, so that .depend generation works. - include U-Boot headers using -idirafter to prevent picking up u-boot/include/errno.h. - use HOSTCFLAGS_NOPED (fw_env.c does not conform to -pedantic). In order to cross-compile tools/env, override the HOSTCC variable as in this example: make tools env HOSTCC=bfin-uclinux-gcc Signed-off-by: NDaniel Hobi <daniel.hobi@schmid-telecom.ch> Tested-by: NDetlev Zundel <dzu@denx.de> Tested-by: NSteve Sakoman <steve.sakoman@linaro.org>
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由 Joakim Tjernlund 提交于
The fixup procedure just stored a constant value in the fixup table rather than just adjusting the table. Although that doesn't seem to do any harm, it prevents relocation more that once. Signed-off-by: NJoakim Tjernlund <Joakim.Tjernlund@transmode.se>
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由 Kumar Gala 提交于
nic and hw structures are allocated via malloc i.e. return memory is not zero initialized. Because of this few structure member like "function pointers" are initialized with garbage values. It may cause problem. for eg. during eth_initialize, dev->write_hwaddr is used. Signed-off-by: NKumar Gala <galak@kernel.crashing.org> Fixed typo. Signed-off-by: NWolfgang Denk <wd@denx.de>
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由 Nobuhiro Iwamatsu 提交于
uli526x driver does not have write_hwaddr function. However, eth stuff executes write_hwaddr function because eth_device structure has not been initialized. Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Ben Warren <biggerbadderben@gmail.com>
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由 Nobuhiro Iwamatsu 提交于
tsi108_eth driver does not have write_hwaddr function. However, eth stuff executes write_hwaddr function because eth_device structure has not been initialized. Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Ben Warren <biggerbadderben@gmail.com>
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由 Nobuhiro Iwamatsu 提交于
pcnet driver does not have write_hwaddr function. However, eth stuff executes write_hwaddr function because eth_device structure has not been initialized. Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Ben Warren <biggerbadderben@gmail.com>
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由 Nobuhiro Iwamatsu 提交于
ns8382x driver does not have write_hwaddr function. However, eth stuff executes write_hwaddr function because eth_device structure has not been initialized. Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Ben Warren <biggerbadderben@gmail.com>
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由 Nobuhiro Iwamatsu 提交于
natsemi driver does not have write_hwaddr function. However, eth stuff executes write_hwaddr function because eth_device structure has not been initialized. Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Ben Warren <biggerbadderben@gmail.com>
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由 Nobuhiro Iwamatsu 提交于
This prevents access to the member of eth_device which is not initialized. Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Ben Warren <biggerbadderben@gmail.com>
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由 Nobuhiro Iwamatsu 提交于
eepro100 driver does not have write_hwaddr function. However, eth stuff executes write_hwaddr function because eth_device structure has not been initialized. Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Ben Warren <biggerbadderben@gmail.com>
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由 Nobuhiro Iwamatsu 提交于
dc2114x driver does not have write_hwaddr function. However, eth stuff executes write_hwaddr function because eth_device structure has not been initialized. Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Ben Warren <biggerbadderben@gmail.com>
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由 Nobuhiro Iwamatsu 提交于
rtl8139 driver does not have write_hwaddr function. However, eth stuff executes write_hwaddr function because eth_device structure has not been initialized. Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Ben Warren <biggerbadderben@gmail.com>
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由 Nobuhiro Iwamatsu 提交于
rtl8169 does not have write_hwaddr function. However, eth stuff executes write_hwaddr function because eth_device structure has not been initialized. Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Ben Warren <biggerbadderben@gmail.com>
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- 13 11月, 2010 3 次提交
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由 Wolfgang Denk 提交于
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由 Wolfgang Denk 提交于
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- 12 11月, 2010 7 次提交
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由 Becky Bruce 提交于
The size of the other bank needed to be added to the br0 setting; this got dropped in the LBC cleanup. Signed-off-by: NBecky Bruce <beckyb@kernel.crashing.org> Tested-by: NWolfgang Denk <wd@denx.de> Acked-by: NWolfgang Denk <wd@denx.de> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Timur Tabi 提交于
Display the 64-byte Reset Configuration Word (RCW) during boot, so that there's no confusion as to what RCW U-boot is using. Reset Configuration Word (RCW): 00000000: 4a500000 00000000 18181818 00008888 00000010: 28402400 00002000 fe800000 01200000 00000020: 00000000 00000000 00000000 000b0000 00000030: 00000000 00000000 00000000 00000000 Signed-off-by: NTimur Tabi <timur@freescale.com> Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
We appear to have different refclk's on the different corenet DS boards so move the define out of the common header. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
CONFIG_SYS_TEXT_BASE setting is common across the 'corenet_ds' board family so move it out of P4080DS.h and into corenet_ds.h Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Priyanka Jain 提交于
SQW/INT pin in RTC can be used for generating square wave(by default) or as interrupt line. U-boot is registering this pin for interrupts. Configuring SQW/INT bit as interrupt line during board initialization to avoid spurious interrupts generated by square wave. Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Haiying Wang 提交于
Introduce a SPL specific CONFIG_SYS_TEXT_BASE_SPL define to be used by the linker. This has similiar semantics to CONFIG_SYS_TEXT_BASE however since SPL is a unqiue image we introduce a new variable to control its text base address. Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 11 11月, 2010 3 次提交
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由 Haiying Wang 提交于
Use CONFIG_SYS_MONITOR_BASE instead of CONFIG_SYS_TEXT_BASE in early init code so we can share the same code with NAND or NOR boot and not have additional ifdefs in here. Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Haiying Wang 提交于
Fix u-boot-nand.lds and u-boot-nand_spl.lds according to: Author: Peter Tyser <ptyser@xes-inc.com> Date: Wed Sep 29 14:05:56 2010 -0500 commit fbe53f59 85xx: Use gc-sections to reduce image size Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 10 11月, 2010 2 次提交
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由 Kumar Gala 提交于
When P2020DS DDR2 was merged it was merged incorrectly and propogated to boards.cfg. Fix this by moving DDR2 config to be associated with P2020DS and not P1_P2_RDB. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Reinhard Meyer 提交于
Supports most types that support Read-Id and the FM25H20. Signed-off-by: NReinhard Meyer <u-boot@emk-elektronik.de> Signed-off-by: NMike Frysinger <vapier@gentoo.org>
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- 30 10月, 2010 4 次提交
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由 Stefano Babic 提交于
Signed-off-by: NStefano Babic <sbabic@denx.de>
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git://git.denx.de/u-boot-marvell由 Wolfgang Denk 提交于
Conflicts: include/configs/km_arm.h Signed-off-by: NWolfgang Denk <wd@denx.de>
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