- 21 2月, 2016 8 次提交
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由 Bin Meng 提交于
This adds basic support to Intel Cougar Canyon 2 board, a board based on Chief River platform with an Ivy Bridge processor and a Panther Point chipset. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
Wrap initialization codes with #ifndef CONFIG_HAVE_FSP #endif, and enable the build for both FSP and non-FSP configurations. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
Intel IvyBridge FSP seems to be buggy that it does not report memory used by FSP itself as reserved in the resource descriptor HOB. The FSP specification does not describe how resource descriptor HOBs are generated by the FSP to describe what memory regions. It looks newer FSPs like Queensbay and BayTrail do not have such issue. This causes U-Boot relocation overwrites the important boot service data which is used by FSP, and the subsequent call to fsp_notify() will fail. To resolve this, we find out the lowest memory base address allocated by FSP for the boot service data when walking through the HOB list in fsp_get_usable_lowmem_top(). Check whether the memory top address is below the FSP HOB list, and if not, use the lowest memory base address allocated by FSP as the memory top address. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org> Tested on link (ivybridge non-FSP) Tested-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
The SMSC SIO1007 superio chipset integrates two ns16550 compatible serial ports for legacy applications, 16 GPIO pins and some other functionalities like power management. This adds a simple driver to enable serial port and handle GPIO. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
IvyBridge FSP package is built with a base address at 0xfff80000, and does not use UPD data region. This adds basic FSP support. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org> Tested on link (ivybridge non-FSP) Tested-by: NSimon Glass <sjg@chromium.org>
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由 Stephen Warren 提交于
Purely by code inspection, it looks like the parameter order to memalign() is swapped; its parameters are (align, size). 4096 is a likely desired alignment, and a variable named size sounds like a size:-) Fixes: 45b5a378 ("x86: Add multi-processor init") Signed-off-by: NStephen Warren <swarren@nvidia.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Tested-by: NBin Meng <bmeng.cn@gmail.com>
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由 Andreas Bießmann 提交于
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
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- 20 2月, 2016 2 次提交
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由 Alexey Brodkin 提交于
With release of ARC HS38 v2.1 new IO coherency engine could be built-in ARC core. This hardware module ensures coherency between DMA-ed data from peripherals and L2 cache. With L2 and IOC enabled there's no overhead for L2 cache manual maintenance which results in significantly improved IO bandwidth. Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>
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由 Alexey Brodkin 提交于
ARC core could be configured with different L1 and L2 (AKA SLC) cache line lengths. At least these values are possible and were really used: 32, 64 or 128 bytes. Current implementation requires cache line to be selected upon U-Boot configuration and then it will only work on matching hardware. Indeed this is quite efficient because cache line length gets hardcoded during code compilation. But OTOH it makes binary less portable. With this commit we allow U-Boot to determine real L1 cache line length early in runtime and use this value later on. This extends portability of U-Boot binary a lot. Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>
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- 19 2月, 2016 25 次提交
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由 Guillaume GARDET 提交于
Since commit fd61d399: spl: mmc: add break statements in spl_mmc_load_image() RAW and FS boot modes are now exclusive again. So, if MMCSD_MODE_RAW fails, the board hangs. This patch allows to try MMCSD_MODE_FS then. It has been tested on a beaglebone black to boot on an EXT partition. Signed-off-by: NGuillaume GARDET <guillaume.gardet@free.fr> Cc: Tom Rini <trini@konsulko.com> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Paul Kocialkowski <contact@paulk.fr> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Simon Glass <sjg@chromium.org> Cc: Matwey V. Kornilov <matwey.kornilov@gmail.com> Acked-by: NNikita Kiryanov <nikita@compulab.co.il>
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由 Gregory CLEMENT 提交于
The Versatile Industrial Communication platform is a community oriented board from Landis + Gyr. It comes with: - an RS-485 port - 2 Ethernet ports - a wireless M-BUS - a 4G modem - a 4MB SPI flash - a 4GB eMMC Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com> [rebase on current TOT] Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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由 Samuel Mescoff 提交于
The SAMA5D2 has a second internal SRAM that can be reassigned as a L2 cache memory. Make sure it is configured as a L2 cache memory when booting from a SPL image. Based on the commit b5ea95ef2b5b from the at91bootstrap repository. Signed-off-by: NSamuel Mescoff <samuel.mescoff@mobile-devices.fr> Reviewed-by: NWenyou Yang <wenyou.yang@atmel.com> Reviewed-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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由 Marek Vasut 提交于
Add support for DENX MA5D4 SoM and MA5D4EVK board, based on the Atmel SAMA5D4 SoC. The SoM contains the SoC, eMMC, SPI NOR, SPI CAN controllers and DRAM, the baseboard contains UART connectors, ethernet port, microSD slot, LCD header, 2x CAN connector and a lot of expansion headers. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Reviewed-by: NHeiko Schocher <hs@denx.de> Reviewed-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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由 Matthias Michel 提交于
New features for smartweb: * switch to hush command parser * change autoboot stop to <ESC><ESC> * allow to write ethaddr Signed-off-by: NMatthias Michel <matthias.michel@siemens.com> Reviewed-by: NSamuel Egli <samuel.egli@siemens.com> Cc: Roger Meier <r.meier@siemens.com> Cc: Heiko Schocher <hs@denx.de> Reviewed-by: NHeiko Schocher <hs@denx.de> Reviewed-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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由 Wenyou Yang 提交于
Due to introducing the PMC_PLLICPR init function, use this function to clean up the code. Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com> Tested-by: NHeiko Schocher <hs@denx.de> Reviewed-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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由 Wenyou Yang 提交于
Due to introducing the PMC_PLLICPR init function, use this function to clean up the code. Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com> Tested-by: NHeiko Schocher <hs@denx.de> Reviewed-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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由 Wenyou Yang 提交于
To avoid the duplicated code, add the PMC_PLLICPR init function. Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com> Tested-by: NHeiko Schocher <hs@denx.de> Reviewed-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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由 Wenyou Yang 提交于
Due to introducing the new PLLB clock handle functions, use these functions to clean up the PLLB enable code. Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com> Reviewed-by: NAndreas Bießmann <andreas.devel@googlemail.com> Tested-by: NHeiko Schocher <hs@denx.de>
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由 Wenyou Yang 提交于
Due to introducing the new PLLB clock handle functions, use these functions to clean up the PLLB enable/disable code. Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com> Reviewed-by: NAndreas Bießmann <andreas.devel@googlemail.com> Tested-by: NHeiko Schocher <hs@denx.de>
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由 Wenyou Yang 提交于
To avoid the duplicated code, add the PLLB handle functions. Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com> Reviewed-by: NAndreas Bießmann <andreas.devel@googlemail.com> Tested-by: NHeiko Schocher <hs@denx.de> [add enable/disable functions to arm920t] Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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由 Wenyou Yang 提交于
Due to introducing the new UTMI PLL clock handle functions, use the functions to reduce the duplicated code. Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com> Tested-by: NHeiko Schocher <hs@denx.de> Reviewed-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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由 Wenyou Yang 提交于
Due to introducing the new UTMI PLL clock handle functions, use these function to reduce the duplicated code. Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com> Tested-by: NHeiko Schocher <hs@denx.de> Reviewed-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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由 Wenyou Yang 提交于
Due to introducing the UTMI PLL enable function, use this function to reduce the duplicated code. Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com> Tested-by: NHeiko Schocher <hs@denx.de> Reviewed-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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由 Wenyou Yang 提交于
To avoid the duplicated code, add the UTMI PLL handle functions, and add PMC_USB init function too. Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com> Tested-by: NHeiko Schocher <hs@denx.de> Reviewed-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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由 Wenyou Yang 提交于
Due to introducing the new peripheral clock handle functions, use these functions to reduce the duplicated code. Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com> Tested-by: NHeiko Schocher <hs@denx.de> [fixup for missing clk.h in at91_emac.c] Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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由 Wenyou Yang 提交于
Due to introducing the new peripheral clock handle functions, use these functions to reduce duplicated code. Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com> Tested-by: NHeiko Schocher <hs@denx.de> [Rebased on current master, fixup for at91rm9200ek] Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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由 Wenyou Yang 提交于
Due to introducing the new peripheral clock handle functions, use these functions to clean up the duplicated code. Meanwhile, remove unneeded header file include, at91_pmc.h. Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com> Tested-by: NHeiko Schocher <hs@denx.de> Reviewed-by: NAndreas Bießmann <andreas.devel@googlemail.com> [fixup for arm920t code] Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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由 Wenyou Yang 提交于
To reduce the duplicated code, add a new file to accommodate the peripheral's and system's clock handle code, shared with the SoCs with different ARM core. Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com> Tested-by: NHeiko Schocher <hs@denx.de> Reviewed-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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由 Wenyou Yang 提交于
Remove unnecessary #ifdef CPU_HAS_PCR. Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com> Tested-by: NHeiko Schocher <hs@denx.de> Reviewed-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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由 Stefan Roese 提交于
With commit a058052c [net: phy: do not read configuration register on reset], phy_reset() will clear the BMCR register. Resulting in bit 12 being cleared (A/N enable). This leads to autonegotiation link problems, at least on the Marvell Armada ClearFog board. I suspect that other boards using this driver will be affected as well. At the of m88e1111s_config(), phy_reset() is called. This is not needed for the PHY to load the changed configuration, as phy_reset() is called a few lines before already. So lets call genphy_restart_aneg() here instead to start the AN correctly. Tested on clearfog. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Stefan Agner <stefan@agner.ch> Cc: Hao Zhang <hzhang@ti.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Andy Fleming <afleming@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Stefan Roese 提交于
Instead of coding the soft PHY reset function multiple times in marvell.c, lets call the common phy_reset() function from phy.c. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Stefan Agner <stefan@agner.ch> Cc: Hao Zhang <hzhang@ti.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Andy Fleming <afleming@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Stephen Warren 提交于
This allows U-Boot to expose UMS and DFU protocols on this port in device mode, or to act as a USB host on the port, using an "OTG" (micro-B to female A host) cable. Signed-off-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Stephen Warren 提交于
This option is no longer used now that DM_USB is enabled. Fixes: 534f9d3f ("dm: tegra: usb: Move USB to driver model") Signed-off-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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- 18 2月, 2016 1 次提交
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由 Simon Glass 提交于
This new feature causes a Kconfig warning on boards without a display enabled. Fix this. Signed-off-by: NSimon Glass <sjg@chromium.org> Acked-by: NAnatolij Gustschin <agust@denx.de> Tested-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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- 17 2月, 2016 4 次提交
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由 Simon Glass 提交于
Remove the old PWM code. Remove calls to CONFIG_LCD functions now that we are using driver model for video. Signed-off-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Simon Glass 提交于
Use the driver-model PWM driver in preference to the old code. Signed-off-by: NSimon Glass <sjg@chromium.org> Acked-by: NAnatolij Gustschin <agust@denx.de> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Simon Glass 提交于
Move this option to Kconfig and clean up the header files. Adjust the only user (the LCD driver) to work with the new driver. Signed-off-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Simon Glass 提交于
Join the two functions which decode the device tree and put them in the ofdata_to_platdata() method. Signed-off-by: NSimon Glass <sjg@chromium.org> Acked-by: NAnatolij Gustschin <agust@denx.de> Signed-off-by: NTom Warren <twarren@nvidia.com>
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