- 09 7月, 2020 40 次提交
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由 Jagan Teki 提交于
DM, DM_SPI and other driver model migration deadlines are expired for this board. Remove it. Cc: Dmitry Lifshitz <lifshitz@compulab.co.il> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Enable DM_SPI, DM_SPI_FLASH for siemens rut board. Build is fine, but not tested. Cc: Samuel Egli <samuel.egli@siemens.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Enable DM_SPI, DM_SPI_FLASH for siemens pxm2 board. Build is fine, but not tested. Cc: Samuel Egli <samuel.egli@siemens.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Enable DM_SPI, DM_SPI_FLASH for siemens thuban board. Build is fine, but not tested. Cc: Samuel Egli <samuel.egli@siemens.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Enable DM_SPI, DM_SPI_FLASH for siemens rastaban board. Build is fine, but not tested. Cc: Samuel Egli <samuel.egli@siemens.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Enable DM_SPI, DM_SPI_FLASH for siemens etamin board. Build is fine, but not tested. Cc: Samuel Egli <samuel.egli@siemens.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Enable DM_SPI, DM_SPI_FLASH for siemens draco board. Build is fine, but not tested. Cc: Samuel Egli <samuel.egli@siemens.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
Enable DM_SPI for am355x igep003x board. Build is fine, but not tested. Cc: Javier Martínez Canillas <javier@dowhile0.org> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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https://gitlab.denx.de/u-boot/custodians/u-boot-i2c由 Tom Rini 提交于
i2c changes for v2020.10 - Add support for I2C controllers found on Octeon II/III and Octeon TX TX2 SoC platforms. - Add I2C controller support for Cortina Access CAxxxx SoCs - new rtc methods, rtc command, and tests - imx_lpi2c: Improve the codes to use private data - stm32f7_i2c.c: Add new compatible "st,stm32mp15-i2c" - stm32f7_i2c.c: Add Fast Mode Plus support - pwm: Add PWM driver for SiFive SoC
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https://gitlab.denx.de/u-boot/custodians/u-boot-marvell由 Tom Rini 提交于
- Armada 38x DDR3 fixes, enhancements (Chris) - Armada 38x UTMI PHY SerDes fix (Chris) - Helios4 update - sync with clearfog (Dennis) - LaCie Kirkwood board rework - enable DM (Simon) - net/mvpp2 memory init fix (Sven)
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由 Sven Auhagen 提交于
Since the mdio code got upstreamed it is not possible to activate network ports on CP110 Master and Slave. The problem is in mvpp2_base_probe which is called for each CP110 and it initializes the buffer area for descs and rx_buffers. This should only happen once though and the bd space is actually set to 0 after the first run of the function. This leads to an error when the second CP110 tries the initialization again and disables all network ports on this CP110. This patch adds a static variable to check if the buffer area is initialized only once globally. Signed-off-by: NSven Auhagen <sven.auhagen@voleatech.de> Reviewed-by: NStefan Roese <sr@denx.de>
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由 Simon Guinot 提交于
This patch enables DM_ETH for the following Kirkwood-based LaCie boards: - d2 Network v2 - Internet Space v2 - 2Big Network v2 - Network Space v2 - Network Space Lite v2 - Network Space Max v2 - Network Space Mini v2 Signed-off-by: NSimon Guinot <simon.guinot@sequanux.org> Reviewed-by: NStefan Roese <sr@denx.de>
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由 Simon Guinot 提交于
This patch enables DM_USB and USB_STORAGE for the following Kirkwood-based LaCie boards: - d2 Network v2 - Internet Space v2 - 2Big Network v2 - Network Space v2 - Network Space Lite v2 - Network Space Max v2 Signed-off-by: NSimon Guinot <simon.guinot@sequanux.org> Reviewed-by: NStefan Roese <sr@denx.de>
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由 Simon Guinot 提交于
This patch switches the SATA driver from mvsata_ide to sata_mv for the following Kirkwood-based LaCie boards: - d2 Network v2 - Internet Space v2 - 2Big Network v2 - Network Space v2 - Network Space Lite v2 - Network Space Max v2 - Network Space Mini v2 Signed-off-by: NSimon Guinot <simon.guinot@sequanux.org> Reviewed-by: NStefan Roese <sr@denx.de>
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由 Simon Guinot 提交于
This patch converts the following Kirkwood-based LaCie boards to DM, DM_SPI and DM_SPI_FLASH: - d2 Network v2 - Internet Space v2 - 2Big Network v2 - Network Space v2 - Network Space Lite v2 - Network Space Max v2 - Network Space Mini v2 Signed-off-by: NSimon Guinot <simon.guinot@sequanux.org> Reviewed-by: NStefan Roese <sr@denx.de> Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Simon Guinot 提交于
The spi0 alias is needed by the environment code to retrieve the SPI flash. This patch adds some -u-boot.dtsi files, providing the spi0 aliases, for all the following Kirkwood-based LaCie boards: - d2 Network v2 - Internet Space v2 - 2Big Network v2 - Network Space v2 - Network Space Lite v2 - Network Space Max v2 - Network Space Mini v2 Note that this -u-boot.dtsi files will be removed as soon as the spi0 aliases will be available in the upstream Linux dtsi files. Signed-off-by: NSimon Guinot <simon.guinot@sequanux.org> Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NStefan Roese <sr@denx.de> Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Dennis Gilmore 提交于
The helios4 is built on the same microsom as the clearfog, by syncing the config we enable the same featureset that exists in the som on the helios4. The current config does not boot as some of the clearfog changes needed to be made on the helios4 also, generally speaking most changes for the clearfog should also be made on the helios4. Signed-off-by: NDennis Gilmore <dennis@ausil.us> Reviewed-by: NStefan Roese <sr@denx.de>
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由 Chris Packham 提交于
When running USB compliance tests on our Armada-385 hardware platforms we have seen some eye mask violations. Marvell's internal documentation says: Based on silicon test results, it is recommended to change the impedance calibration threshold setting to 0x6 prior to calibration. Port changes from Marvell's u-boot fork[1] to address this. [1] - https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/a6221551Signed-off-by: NChris Packham <judge.packham@gmail.com> Reviewed-by: NStefan Roese <sr@denx.de>
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由 Chris Packham 提交于
Fix spelling of Alignment. Signed-off-by: NChris Packham <judge.packham@gmail.com> Reviewed-by: NStefan Roese <sr@denx.de>
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由 Chris Packham 提交于
Measurements on actual hardware shown that the read ODT is early by 3 clocks. Adjust the calculation to avoid this. Signed-off-by: NChris Packham <chris.packham@alliedtelesis.co.nz> [upstream https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/22] Signed-off-by: NChris Packham <judge.packham@gmail.com> Tested-by: NBaruch Siach <baruch@tkos.co.il> Reviewed-by: NStefan Roese <sr@denx.de>
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由 Chris Packham 提交于
In the Armada 385 functional spec (MV-S109094-00 Rev. C) the read sample delay fields are 5 bits wide. Use the correct bitmask of 0x1f when extracting the value. Signed-off-by: NChris Packham <chris.packham@alliedtelesis.co.nz> [upstream https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/22] Signed-off-by: NChris Packham <judge.packham@gmail.com> Reviewed-by: NStefan Roese <sr@denx.de>
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由 Yash Shah 提交于
Adds a PWM driver for PWM chip present in SiFive's HiFive Unleashed SoC This driver is simple port of Linux pwm sifive driver from Linux v5.6 commit: 9e37a53eb051 ("pwm: sifive: Add a driver for SiFive SoC PWM") Signed-off-by: NYash Shah <yash.shah@sifive.com> Reviewed-by: NHeiko Schocher <hs@denx.de>
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由 Yash Shah 提交于
DT documentation for PWM controller added from Linux v5.6 commit: daa78cc3408e ("pwm: sifive: Add DT documentation for SiFive PWM Controller") Signed-off-by: NYash Shah <yash.shah@sifive.com> Reviewed-by: NHeiko Schocher <hs@denx.de>
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由 Patrick Delaunay 提交于
Read SYSCFG bindings to set Fast Mode Plus bits if Fast Mode Plus speed is selected. Handle the stm32mp15 specific compatible to handle FastMode+ registers handling which is different on the stm32mp15 compared to the stm32f7 or stm32h7. Indeed, on the stm32mp15, the FastMode+ set and clear registers are separated while on the other platforms (F7 or H7) the control is done in a unique register. Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com> Reviewed-by: NHeiko Schocher <hs@denx.de>
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由 Patrick Delaunay 提交于
Add a new compatible "st,stm32mp15-i2c" introduced in Linux kernel v5.8 Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com> Reviewed-by: NHeiko Schocher <hs@denx.de>
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由 Rasmus Villemoes 提交于
Add tests of the "list", "read" and "write" subcommands of the rtc shell command. Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NHeiko Schocher <hs@denx.de> Signed-off-by: NRasmus Villemoes <rasmus.villemoes@prevas.dk>
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由 Rasmus Villemoes 提交于
In order to allow adding unit tests of the rtc command, add it to the various sandbox defconfigs. Signed-off-by: NRasmus Villemoes <rasmus.villemoes@prevas.dk>
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由 Rasmus Villemoes 提交于
Define a few aux registers and check that they can be read/written individually. Also check that one can access the time-keeping registers directly and get the expected results. Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NHeiko Schocher <hs@denx.de> Signed-off-by: NRasmus Villemoes <rasmus.villemoes@prevas.dk>
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由 Rasmus Villemoes 提交于
It's more natural that any write that happens to touch the reset register should cause a reset, rather than just a write that starts at that offset. Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NHeiko Schocher <hs@denx.de> Signed-off-by: NRasmus Villemoes <rasmus.villemoes@prevas.dk>
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由 Rasmus Villemoes 提交于
The current set method is broken; a simple test case is to first set the date to something in April, then change the date to 31st May: => date 040412122020.34 Date: 2020-04-04 (Saturday) Time: 12:12:34 => date 053112122020.34 Date: 2020-05-01 (Friday) Time: 12:12:34 or via the amending of the existing rtc_set_get test case similarly: $ ./u-boot -T -v => ut dm rtc_set_get Test: dm_test_rtc_set_get: rtc.c expected: 31/08/2004 18:18:00 actual: 01/08/2004 18:18:00 The problem is that after each register write, sandbox_i2c_rtc_complete_write() gets called and sets the internal time from the current set of registers. However, when we get to writing 31 to mday, the registers are in an inconsistent state (mon is still 4), so the mktime machinery ends up translating April 31st to May 1st. Upon the next register write, the registers are populated by sandbox_i2c_rtc_prepare_read(), so the 31 we just wrote to mday gets overwritten by a 1. Fix it by writing all registers at once, and for consistency, update the get method to retrieve them all with one "i2c transfer". Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NHeiko Schocher <hs@denx.de> Signed-off-by: NRasmus Villemoes <rasmus.villemoes@prevas.dk>
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由 Rasmus Villemoes 提交于
Mostly as an aid for debugging RTC drivers, provide a command that can be used to read/write arbitrary registers (assuming the driver provides the read/write methods or their single-register-at-a-time variants). Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NHeiko Schocher <hs@denx.de> Signed-off-by: NRasmus Villemoes <rasmus.villemoes@prevas.dk>
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由 Rasmus Villemoes 提交于
Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NHeiko Schocher <hs@denx.de> Signed-off-by: NRasmus Villemoes <rasmus.villemoes@prevas.dk>
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由 Rasmus Villemoes 提交于
This simply consists of renaming the existing pcf2127_read_reg() helper to follow the naming of the other methods (i.e. pcf2127_rtc_<method name>) and changing the type of its "len" parameter. Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NHeiko Schocher <hs@denx.de> Signed-off-by: NRasmus Villemoes <rasmus.villemoes@prevas.dk>
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由 Rasmus Villemoes 提交于
Similar to how the dm_rtc_{read,write} functions fall back to using the {read,write}8 methods, do the opposite in the rtc_{read,write}8 functions. This way, each driver only needs to provide either ->read8 or ->read to make both rtc_read8() and dm_rtc_read() work - without this, a driver that provides ->read() would most likely just duplicate the logic here for implementing a ->read8() method in term of its ->read() method. The same remarks of course apply to the write case. Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NHeiko Schocher <hs@denx.de> Signed-off-by: NRasmus Villemoes <rasmus.villemoes@prevas.dk>
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由 Rasmus Villemoes 提交于
Similar to dm_rtc_read(), introduce a helper that allows the caller to write multiple consecutive 8-bit registers with one call. If the driver provides the ->write method, use that, otherwise loop using ->write8. Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NHeiko Schocher <hs@denx.de> Signed-off-by: NRasmus Villemoes <rasmus.villemoes@prevas.dk>
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由 Rasmus Villemoes 提交于
Some users may want to read multiple consecutive 8-bit registers. Instead of each caller having to implement the loop, provide a dm_rtc_read() helper. Also, allow a driver to provide a ->read method, which can be more efficient than reading one register at a time. Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NHeiko Schocher <hs@denx.de> Signed-off-by: NRasmus Villemoes <rasmus.villemoes@prevas.dk>
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由 Ye Li 提交于
Current driver calls the devfdt_get_addr to get the base address of lpi2c controller in each sub-functions. Since the devfdt_get_addr accesses the DTB and translate the address, it introduces much overhead. Improve the codes to use private variable which has recorded the base address from probe. Signed-off-by: NYe Li <ye.li@nxp.com> Reviewed-by: NPeng Fan <peng.fan@nxp.com>
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由 Alex Nemirovsky 提交于
Add I2C board support for Cortina Access Presidio Engineering Board Signed-off-by: NAlex Nemirovsky <alex.nemirovsky@cortina-access.com> CC: Heiko Schocher <hs@denx.de> Reviewed-by: NHeiko Schocher <hs@denx.de>
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由 Arthur Li 提交于
Add I2C controller support for Cortina Access CAxxxx SoCs Signed-off-by: NArthur Li <arthur.li@cortina-access.com> Signed-off-by: NAlex Nemirovsky <alex.nemirovsky@cortina-access.com> CC: Heiko Schocher <hs@denx.de> Reviewed-by: NHeiko Schocher <hs@denx.de> hs: fixed build error, add include log.h
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由 Suneel Garapati 提交于
Add support for I2C controllers found on Octeon II/III and Octeon TX TX2 SoC platforms. Signed-off-by: NAaron Williams <awilliams@marvell.com> Signed-off-by: NSuneel Garapati <sgarapati@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NHeiko Schocher <hs@denx.de> Reviewed-by: NRayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
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