Like data training in other sdram types, mr detection need
to taken care for lpddr4 with looped rank and associated
channel to make sure the proper configuration held.

Once the mr detection successful for active and configured
rank with channel number, the same can later reused during
actual LPDDR4 initialization.

So, add code to support for it.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Signed-off-by: NYouMin Chen <cym@rock-chips.com>
Reviewed-by: NKever Yang <Kever.yang@rock-chips.com>

data training can be even required for lpddr4 and we
need to keep the lpddr4 code to compile only for relevant
boards which do support lpddr4.

For this requirement, and for code readability handle
data training via sdram_rk3399_ops and same will update
in future while supporting lpddr4 code.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NKever Yang <Kever.yang@rock-chips.com>

data training is using chan_info as first argument with
channel number as second argument instead of that use
dram_info as first argument so-that we can get the
chan_info at data training definition.

This was the argument handling is meaningful, readable
and it would help to add similar data training for
lpddr4 in future.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NKever Yang <Kever.yang@rock-chips.com>

Update vref_mode_ac for lpddr4 based on VDDQ/3/2=16.8%
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Signed-off-by: NYouMin Chen <cym@rock-chips.com>
Reviewed-by: NKever Yang <Kever.yang@rock-chips.com>

The mode_sel on lpddr4 value is depending on IO settings
of rd_vref.

Add support for it.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Signed-off-by: NYouMin Chen <cym@rock-chips.com>

The vref_mode_dq, vref_value_dq on lpddr4 value is depending
on IO settings of rd_vref.

Add support for it.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Signed-off-by: NYouMin Chen <cym@rock-chips.com>
Reviewed-by: NKever Yang <Kever.yang@rock-chips.com>

For base.odt 1 the lpddr4 tsel_rd_en value is depending
on IO settings of rd_odt_en.

Add support for it.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Signed-off-by: NYouMin Chen <cym@rock-chips.com>
Reviewed-by: NKever Yang <Kever.yang@rock-chips.com>

CTL 145, 146, 159, 160 registers are used to configure
soc odt on rk3399.

These soc odt values are updated from CS0_MR22_VAL and
CS1_MR22_VAL and for lpddr4 these values ORed with
tsel_rd_select_n.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Signed-off-by: NYouMin Chen <cym@rock-chips.com>

tsel contrl clock drives are required to configure PHY
929, 939 controls drive settings.

Add support for these control clock for all dramtype
sdrams.

Thse control clock drives are configure via tsel_ckcs_select_p
and tsel_ckcs_select_n variables.

tsel_ckcs_select_n is PHY_DRV_ODT_34_3 value where as
tsel_ckcs_select_p is retrived from IO settings for lpddr4
and rest uses PHY_DRV_ODT_34_3.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Signed-off-by: NYouMin Chen <cym@rock-chips.com>
Reviewed-by: NKever Yang <Kever.yang@rock-chips.com>

Now we have IO settings available for all supported sdram
frequencies, so retrieve these IO settings and make used
for LPDDR4 ds odt configuration.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Signed-off-by: NYouMin Chen <cym@rock-chips.com>

Add IO settings for dram ctl and phy.

IO settings are useful for configuring ctl, phy odt, vref,
mr5, mode select and other needed input output operations
for lpddr4 or any other dramtype sdram.

Right now, this patch added IO setting for all supported
sdram frequencies.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Signed-off-by: NYouMin Chen <cym@rock-chips.com>
Reviewed-by: NKever Yang <Kever.yang@rock-chips.com>

The hardware for LPDDR4 with
- CLK0P/N connect to lower 16-bits
- CLK1P/N connect to higher 16-bits

and usually dfi dram clk is configured via CLK1P/N, so
disabling dfi dram clk will disable the CLK1P/N as well.

So, add patch to not to disable dfi dram clk for lpddr4,
with rank 1.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Signed-off-by: NYouMin Chen <cym@rock-chips.com>
Reviewed-by: NKever Yang <Kever.yang@rock-chips.com>

tsel write ca_p and ca_n values need to write on PHY 544, 672
and 800 to configure ds odt.

Configure the same PHY register for lpddr4 would require a mask
value of (300 << 8).

Add support for it.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Signed-off-by: NYouMin Chen <cym@rock-chips.com>
Reviewed-by: NKever Yang <Kever.yang@rock-chips.com>

Assign desired cs_map values for lpddr4 during set memory map.

Initial cs_map values is based on the sdram parameters, so
the same will adjusted based dramtype as LPDDR4.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Signed-off-by: NYouMin Chen <cym@rock-chips.com>

Configure PHY RX_CM_INPUT for lpddr4 during phy IO config.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Signed-off-by: NYouMin Chen <cym@rock-chips.com>
Reviewed-by: NKever Yang <Kever.yang@rock-chips.com>

Configure SLEWP_EN, SLEWN_EN for lpddr4 during phy IO config.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Signed-off-by: NYouMin Chen <cym@rock-chips.com>

Configure BOOSTP_EN, BOOSTN_EN for lpddr4 during phy IO config.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Signed-off-by: NYouMin Chen <cym@rock-chips.com>
Reviewed-by: NKever Yang <Kever.yang@rock-chips.com>

PHY_898, PHY_919 would require to configure PHY LP4 boot
pll control and ca for lpddr4.

So, configure the same in pctl_cfg for LPDDR4.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Signed-off-by: NYouMin Chen <cym@rock-chips.com>
Reviewed-by: NKever Yang <Kever.yang@rock-chips.com>

It is possible in lpddr4 dram, where both the channels would
start at same time with ZQ Cal Start. If it uses ZQ Call start
then it will use RZQ.

For example LPDDR4 366 Dual-Die, Quad-Channel Package, RZQ maybe
connect to both channel. If ZQ Cal Start at the same time,
it will use the same RZQ.

It is not a problem of using RZQ in both the channels, but can not
use at the same time.

So, to avoid this, we have an option of dram tINIT3 value for
increasing the frequency for channel 1.

This patch increase the available tINIT3 with existing running
dram frequency.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Signed-off-by: NYouMin Chen <cym@rock-chips.com>
Reviewed-by: NKever Yang <Kever.yang@rock-chips.com>

lpddr4 has PLL bypass mode during phy initialization phase,
which does all pll configurations.

So no need to wait explicitly during pctl config.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Signed-off-by: NYouMin Chen <cym@rock-chips.com>
Reviewed-by: NKever Yang <Kever.yang@rock-chips.com>

mode_sel assignment is based on dram type.

In phy_io_config, already have vref setting based
on the dram type, so move this mode_sel assignment
on vref setting area.

No functionality change.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NKever Yang <Kever.yang@rock-chips.com>

Add rank_mask based on the rank number for lpddr4.

This would keep the wdql data training loop based on the
desired rank mask value instead of looping for all values.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Signed-off-by: NYouMin Chen <cym@rock-chips.com>
Reviewed-by: NKever Yang <Kever.yang@rock-chips.com>

Add rank_mask based on the rank number for lpddr4.

This would keep the ca data training loop based on the
desired rank mask value instead of looping for all values.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Signed-off-by: NYouMin Chen <cym@rock-chips.com>
Reviewed-by: NKever Yang <Kever.yang@rock-chips.com>

Supporting LPDDR4 code support in RK3399 would increases
the size of SPL/TPL.

So add kconfig entry for RK3399 LPDDR4 code so-that
the boards have LPDDR4 can enable them via defconfig.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NKever Yang <Kever.yang@rock-chips.com>

Some dramtypes like lpddr4 initialization would required to
configure phy IO even after pctl_cfg and after set_ds_odt.

For those cases the set_ds_odt would be an initial call to
setup the phy.

To satisfy all the cases, trigger phy IO from set_ds_odt.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NKever Yang <Kever.yang@rock-chips.com>

Add DdrMode structure with associated bit fields.

These would help to reconfigure sdram capabilities during
lpddr4 setup related configs.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NKever Yang <Kever.yang@rock-chips.com>

Add DdrTimingC0 structure with associated bit fields.

These would help to reconfigure sdram capabilities during
lpddr4 setup related configs.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NKever Yang <Kever.yang@rock-chips.com>

Add dram config macro for handling ddr version number.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Signed-off-by: NYouMin Chen <cym@rock-chips.com>
Reviewed-by: NKever Yang <Kever.yang@rock-chips.com>

cs0_row, cs1_row and cs1_col needs more bits to show its
correct value, update to make use of both sys_reg2,
sys_reg3.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Signed-off-by: NYouMin Chen <cym@rock-chips.com>
Reviewed-by: NKever Yang <Kever.yang@rock-chips.com>
(Squash similar patches into one patch)
Signed-off-by: NKever Yang <Kever.yang@rock-chips.com>

Use dram config variable name as sys_reg2 instead of sys_reg
since the final variable value is to written into a pmugrf
register named as sys_reg2.

This reflect the both variable and associated register
names are same and also help to add next sys_reg's to
add it in future.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Signed-off-by: NYouMin Chen <cym@rock-chips.com>
Reviewed-by: NKever Yang <Kever.yang@rock-chips.com>

Add simplified and meaningful macro for all setting.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Signed-off-by: NYouMin Chen <cym@rock-chips.com>
Reviewed-by: NKever Yang <Kever.yang@rock-chips.com>
(Squash the similar patches into 1 patch)
Signed-off-by: NKever Yang <Kever.yang@rock-chips.com>

This would help to debug the sdram base parameters while
debugging existing chip or while supporting new sdram type.

It require explicit enablement of CONFIG_RAM_ROCKCHIP_DEBUG
for showing the debug prints.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NKever Yang <Kever.yang@rock-chips.com>

Right now the rk3399 sdram driver assume that the board
has configured with 2 channels, so any possibility to
enable single channel on the same driver will encounter
channel #1 data training failure.

Log:
U-Boot TPL board init
sdram_init: data training failed
rk3399_dmc_init DRAM init failed -5

So, add an algorithm that can capable to compute the active
or configured rank with associated channel like
a) do rank loop to compute the active rank, with associated
   channel numbers
b) then, succeed the data training only for configured channel
c) preserve the rank for given channel
d) do channel loop for setting the active channel
e) if given rank is zero or inactive on the specific channel,
   clear the timings for the associated channel
f) finally, return error if number of channels is zero

Tested in NanoPI-NEO4 since it support single channel sdram
configuration.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Signed-off-by: NYouMin Chen <cym@rock-chips.com>
Reviewed-by: NKever Yang <Kever.yang@rock-chips.com>
(add PI_READ_GATE_TRAINING for LPDDR3 to support rk3399-evb case)
Signed-off-by: NKever Yang <Kever.yang@rock-chips.com>

Add stride computation for the sdram which support
single channel a

This configuration available in NanoPi NEO4 and the
same can work with existing rk3399-sdram-ddr3-1866.dtsi
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Signed-off-by: NYouMin Chen <cym@rock-chips.com>
Reviewed-by: NKever Yang <Kever.yang@rock-chips.com>

stride value from sdram timings can be computed dynamically
based on the determined capacity for the given channel.

Right now these stride values are taken as part of sdram timings
via dtsi, but it possible to use same timings dtsi for given
frequency even though the configured board sdram do support
single channel with different size by dynamically detect the
stride value.

Example, NanoPi NEO4 do have DDR3-1866, but with single channel
and 1GB size with dynamic stride detection it is possible to
use existing rk3399-sdram-ddr3-1866.dtsi whose stride,
number of channels and capacity it support is d efferent.

So, add initial support to calculate the stride value for
2 channels sdram, which is available by default on existing
boards.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Signed-off-by: NYouMin Chen <cym@rock-chips.com>
Reviewed-by: NKever Yang <Kever.yang@rock-chips.com>

Add code to print the channel stride, this would help to
print the stride of associated channel.

Here is sample print on LPDDR4, 50MHz.
256B stride
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Signed-off-by: NYouMin Chen <cym@rock-chips.com>
Reviewed-by: NKever Yang <Kever.yang@rock-chips.com>

Add code to get the channel capacity, this would help to
print the capacity of specific channel.

Here is sample print on LPDDR4, 50MHz channel 0
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Signed-off-by: NYouMin Chen <cym@rock-chips.com>
Reviewed-by: NKever Yang <Kever.yang@rock-chips.com>

Add sdram ddr info print support, this would help to
observe the sdram base parameters.

Here is sample print on LPDDR4, 50MHz channel 0
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Signed-off-by: NYouMin Chen <cym@rock-chips.com>
Reviewed-by: NKever Yang <Kever.yang@rock-chips.com>

Add sdram driver to handle debug across rockchip SoCs.

This would help to improve code debugging feature for
sdram drivers in rockchip family, whoever wants to
debug the driver should call these core debug code on
their respective platform sdram drivers.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Signed-off-by: NYouMin Chen <cym@rock-chips.com>
Reviewed-by: NKever Yang <Kever.yang@rock-chips.com>

Add printdec, this would help to print an
output a decimalism value.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Signed-off-by: NYouMin Chen <cym@rock-chips.com>
Reviewed-by: NKever Yang <Kever.yang@rock-chips.com>