Keep dtsi in sync with mainline kernel.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Remove unused xlnx,id property because it is not the part of
DT binding.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Updating required device tree changes as per mainlined driver
from 4.6 kernel.
Signed-off-by: NBharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Previously, it was assumed that there is a 1:1 mapping between
PM ID defined in the platform firmware and a PM domain. However, there
can be a situation where multiple PM IDs belong to a single PM domain
(e.g. PM IDs for GPU and two pixel processors correspond to a single
PM domain).

This patch adds support for assigning more than one PM ID to
a single PM domain.

Updated documentation accordingly.

Assigned pixel processors PM IDs to GPU PM domain.
Signed-off-by: NFilip Drazic <filip.drazic@aggios.com>
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Signed-off-by: NFilip Drazic <filip.drazic@aggios.com>
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Signed-off-by: NFilip Drazic <filip.drazic@aggios.com>
Acked-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

DDR power states are handled by the PM firmware, so this domain is
redundant. Also, since there is no device using this PM domain,
it will be powered off during boot, which is wrong.
Signed-off-by: NFilip Drazic <filip.drazic@aggios.com>
Acked-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

i2c device is just level shifter. Remove reference from dts.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add dcc to dtsi for supporting system without serial port.
DCC is enabled by default on ZynqMP.
Adding dcc to zcu100 and zcu102 which were tested.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

There is gpio push button on MIO22. Add it to DTS to have full board
description.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Show user that Linux is alive on the board.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

This patch enables can1 for ep108.
Signed-off-by: NNaga Sureshkumar Relli <nagasure@xilinx.com>
Reviewed-by: NKedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Added clks for ep108 platform.
Signed-off-by: NVNSL Durga <vnsldurg@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Zynqmp DMA driver expects two clocks (main clock and apb clock)
LPDDMA clock cofiguration is missing for the same in the
zynqmp-clk.dtsi file.

This patch updates for the same.
Reported-by: NSai Pavan Boddu <saipava@xilinx.com>
Signed-off-by: NKedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

DTC 1.4.2 reports these warnings:
Warning (unit_address_vs_reg): Node /amba_apu has a reg or ranges
property, but no unit name
Warning (unit_address_vs_reg): Node /amba has a reg or ranges property,
but no unit name
Warning (unit_address_vs_reg): Node /amba/usb@fe200000 has a unit name,
but no reg property
Warning (unit_address_vs_reg): Node /amba/usb@fe300000 has a unit name,
but no reg property
Warning (unit_address_vs_reg): Node
/amba/dma@fd4c0000/dma-video0channel@fd4c0000 has a unit name, but no
reg property
Warning (unit_address_vs_reg): Node
/amba/dma@fd4c0000/dma-video1channel@fd4c0000 has a unit name, but no
reg property
Warning (unit_address_vs_reg): Node
/amba/dma@fd4c0000/dma-video2channel@fd4c0000 has a unit name, but no
reg property
Warning (unit_address_vs_reg): Node
/amba/dma@fd4c0000/dma-graphicschannel@fd4c0000 has a unit name, but no
reg property
Warning (unit_address_vs_reg): Node
/amba/dma@fd4c0000/dma-audio0channel@fd4c0000 has a unit name, but no
reg property
Warning (unit_address_vs_reg): Node
/amba/dma@fd4c0000/dma-audio1channel@fd4c0000 has a unit name, but no
reg property
Warning (unit_address_vs_reg): Node /memory has a reg or ranges
property, but no unit name

This patch is fixing them.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

DTC 1.4.2 reports these warnings:
Warning (unit_address_vs_reg): Node /memory has a reg or ranges
property, but no unit name
Warning (unit_address_vs_reg): Node /pmu has a reg or ranges property,
but no unit name
Warning (unit_address_vs_reg): Node /fixedregulator@0 has a unit name,
but no reg property

This patch is fixing them.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Correct the sdhci minimum frequency for ep platform.
It should be right shift instead of left shift operand.
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Autogenerated files contain casting issues and missing function
declaration and even usleep implementation. Suppress them for now
till these files are fixed.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Do not setup use_alt bit which copy alternative boot mode to
boot mode. The reason is that this bit is cleared after POR
but not after any software reset which will cause
that after SW reset bootrom will look for different boot image.

This patch setups alternative boot mode selection (purely SW
handling) and extends code to read this alternative boot mode first and
use it if it is setup.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add support for SD1 with level shifters bootmode.
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

The new FW interface returns the IDCODE and version register, leaving
extracting bitfields to the caller.

Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Zynq 7000S (Single A9 core) devices is using different ID code.
This patch adds this new codes and assign them.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Correct the SGMII enable bit position to 27 instead
of 31.
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Modify the nwcfg bit definitions to have 32-bit
by removing the extra nibble.
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Clear ecc ON bit while sending read command as all types
of read command(like reading spare) doesnt need ECC to be
enabled. It has been anyway taken care in other places
whereever required using arasan_nand_enable_ecc().
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

This patch adds support to check the buswidth on nand flash
at runtime based on nand MIO configurations done by FSBL.

User needs to correctly configure the MIO's based on the
buswidth supported by the nand flash which is present on the board.

Added nand8 and nand16 @periph names on slcr driver.
Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Enable zynq Nand flash controller driver for a zynq ZC770
XM011(dc2) board.
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add nand flash controller driver support for zynq SoC.
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

The topic-miami SoMs contain a Zynq xc7z015 or xc7z030 SoC, 1GB DDR3L RAM,
32MB QSPI NOR flash and 256MB NAND flash.

The topic-miamiplus SoMs contain a Zynq xc7z035, xc7z045 or xc7z100 SoC,
2x 1GB DDR3L RAM, 64MB dual-parallel QSPI flash, clock sources
and a fan controller.

The "Florida" carrier boards add SD, USB, ethernet and other interfaces.
Signed-off-by: NMike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add a string description for SYS_VENDOR to allow configuring boards from
other vendors than just "xilinx".
Signed-off-by: NMike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Current Makefile.spl passes -R parameter which is not empty
and pointing to ./ folder.
"./tools/mkimage -T zynqmpimage -R ./"" -d spl/u-boot-spl.bin
spl/boot.bin"
That's why mkimage is trying to parse ./ file and generate
register init which is wrong.
Check that passed filename is regular file. If not do not work with it.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

The Zynq/ZynqMP boot.bin file contains a region for register initialization
data. Filling in proper values in this table can reduce boot time
(e.g. about 50ms faster on QSPI boot) and also reduce the size of
the SPL binary.

The table is a simple text file with register+data on each line. Other
lines are simply skipped. The file can be passed to mkimage using the
"-R" parameter.

It is recommended to add reg init file to board folder.
For example:
CONFIG_BOOT_INIT_FILE="board/xilinx/zynqmp/xilinx_zynqmp_zcu102/reg.int
Signed-off-by: NMike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Signed-off-by: NTom Rini <trini@konsulko.com>

Ian has not had any time for sunxi for some time now and I'm
in the same situation now, so I'm stepping down as sunxi
custodian and marking the sunxi support as Orphan.

Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

Compiling the 'bmp' command with DM and having one of the following macros
enabled:

CONFIG_BMP_16BPP, CONFIG_BMP_24BPP ONFIG_BMP_32BPP

generates this error:

drivers/video/video_bmp.c: In function ‘video_bmp_display’:
drivers/video/video_bmp.c:315:22: error: ‘lcd_line_length’ undeclared (first use in this function)
    fb -= width * 2 + lcd_line_length;
                          ^

This patch moves to using the correct variable instead and enables the
'bmp' command for DM again.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Anatolij Gustschin <agust@denx.de>

If mac-address is changed using "setenv ethaddr ...." command the new
mac-adress also must be written into the responsible ethernet driver.
This fixes the legacy ethernet handling.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Hannes Schmelzer <oe5hpm@oevsv.at>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: NHannes Schmelzer <oe5hpm@oevsv.at>

Fix the divider calculation logic to choose a value so that the
resulting baudrate is either equal to or closest possible baudrate less
than the requested value. While at that, cleanup ti_spi_set_speed().
Signed-off-by: NVignesh R <vigneshr@ti.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>

Update the spi-max-frequency property of m25p80 flash slave to match
that of TI QSPI controller node, so that QSPI operations happen at
maximum supported frequency of 76.8MHz.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Reviewed-by: NJagan Teki <jteki@openedev.com>

Only a certain set of PLLM/D values are recommended to configure the DDR
at the required speeds for a given clock input frequency. Updating these
values as specified in Data Sheet[1] Table 5-18

[1] http://www.ti.com/lit/ds/symlink/66ak2g02.pdfSigned-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>