- 14 4月, 2017 14 次提交
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由 Dalon Westergreen 提交于
This removes the default environment from the de1 headers and instead uses the common environment provided in socfpga_common.h which now uses distro boot. This board does not have a devicetree in the upstream kernel source so set devicetree to socfpga_cyclone5_de1_soc.dtb. Signed-off-by: NDalon Westergreen <dwesterg@gmail.com> Acked-by: NMarek Vasut <marex@denx.de> -- Changes in V2: - Remove unneeded CONFIG_BOOTFILE - set devicetree name to match socfpga_{fpga model}_{board model}.dts pattern
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由 Dalon Westergreen 提交于
This removes the default environment from the C5 SoCDK headers and instead uses the common environment provided in socfpga_common.h which now uses distro boot. In addition to the above, add support to boot from the custom a2 type partition. Change default devicetree name to match devicetree name in upstream kernel source. Signed-off-by: NDalon Westergreen <dwesterg@gmail.com> Acked-by: NMarek Vasut <marex@denx.de> -- Changes in v2: - Remove unneeded CONFIG_BOOTFILE
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由 Dalon Westergreen 提交于
This removes the default environment from the A5 socdk headers and instead uses the common environment provided in socfpga_common.h which now uses distro boot. Add support to boot from the custom a2 type partition. Change default devicetree name to match devicetree name in upstream kernel source. Signed-off-by: NDalon Westergreen <dwesterg@gmail.com> Acked-by: NMarek Vasut <marex@denx.de> -- Changes in v3: - Fix small typo in defconfig, missing "C" Changes in v2: - Remove unneeded CONFIG_BOOTFILE - Fix dtb name a5config test Signed-off-by: NDalon Westergreen <dwesterg@gmail.com>
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由 Dalon Westergreen 提交于
This removes the default environment from the de0 headers and instead uses the common environment provided in socfpga_common.h which now uses distro boot. In addition to the above, add support to boot from the custom a2 type partition Signed-off-by: NDalon Westergreen <dwesterg@gmail.com> Acked-by: NMarek Vasut <marex@denx.de> -- Changes in v2: - Remove unneeded CONFIG_BOOTFILE
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由 Dalon Westergreen 提交于
This adds a common environment and support for distro boot in the common socfpga header. Signed-off-by: NDalon Westergreen <dwesterg@gmail.com> Acked-by: NMarek Vasut <marex@denx.de> -- Changes in v5: - Per Frank, to support OpenSuse the ENV must be after the GPT Changes in v4: - Move env back to being right after the MBR Changes in v3: - fix spacing between asterix - remove verify=n as a default setting Changes in v2: - Remove unneeded CONFIG_BOOTFILE and fdt_addr - cleanup spacing in MMC env size common Signed-off-by: NDalon Westergreen <dwesterg@gmail.com>
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由 Ley Foon Tan 提交于
Convert Altera DDR SDRAM driver to use Kconfig method. Enable ALTERA_SDRAM by default if it is on Gen5 target. Arria 10 will have different driver. Signed-off-by: NTien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>
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由 Ley Foon Tan 提交于
Add compatible strings for Intel Arria 10 SoCFPGA device. Signed-off-by: NTien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>
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由 Marek Vasut 提交于
Disable the OC test on MCVEVK as the old PHY version does not provide this information. This fixes the USB OTG operation. Signed-off-by: NMarek Vasut <marex@denx.de>
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由 Marek Vasut 提交于
Add default DFU altinfo for eMMC. Signed-off-by: NMarek Vasut <marex@denx.de>
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由 Marek Vasut 提交于
There is no point in having such gargantuan buffer, it only requires huge malloc area. Reduce the DFU buffer size. Signed-off-by: NMarek Vasut <marex@denx.de>
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由 Marek Vasut 提交于
The board is now manufactured by Aries Embedded GmbH , rename it. Signed-off-by: NMarek Vasut <marex@denx.de>
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由 Chee, Tien Fong 提交于
Commit ce62e57f ("ARM: boot0 hook: remove macro, include whole header file") miss out cleaning macro in this header file, and this has broken implementation of a boot header capability in socfpga SPL. Remove the macro in this file, and recovering it back to proper functioning. Fixes: ce62e57f ("ARM: boot0 hook: remove macro, include whole header file") Signed-off-by: NChee, Tien Fong <tien.fong.chee@intel.com>
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由 Georges Savoundararadj 提交于
With the port C enabled, we can read the GPI input state of: * the DIP switches (USER_DIPSW_HPS[3:0]/HPS_GPI[7:4]) * the push buttons (USER_PB_HPS[3:0]/HPS_GPI[11:8]) Signed-off-by: NGeorges Savoundararadj <savoundg@gmail.com> Signed-off by: Sid-Ali Teir <git.syedelec@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Marek Vasut <marex@denx.de>
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由 Stephen Arnold 提交于
This patch adds the steps to manually (re)build a Quartus FPGA project, generate the required BSP glue, and update u-boot handoff files for mainline SPL support. Requires Quartus toolchain and current U-Boot. Signed-off-by: NSteve Arnold <stephen.arnold42@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de>
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- 11 4月, 2017 3 次提交
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由 Alexey Brodkin 提交于
As reported in STAR 9001165532, an SLC control reg read (for checking busy state) right after SLC invalidate command may incorrectly return NOT busy causing software to NOT spin-wait while operation is underway. (and for some reason this only happens if L1 cache is also disabled - as required by IOC programming model) Suggested workaround is to do an additional Control Reg read, which ensures the 2nd read gets the right status. Same fix made in Linux kernel: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c70c473396cbdec1168a6eff60e13029c0916854Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>
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由 Stefan Agner 提交于
For some reason Python 3 seems to think it does not need to build the library. Using the --force parameter makes sure that the library gets built always. This is especially important since we move the library in the next step of the Makefile, hence forcing a rebuild every time the higher level Makefile triggers a rebuild is required to make sure the library is always there. Signed-off-by: NStefan Agner <stefan.agner@toradex.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
This a few minor changes down from upstream since the last sync. Signed-off-by: NSimon Glass <sjg@chromium.org>
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- 10 4月, 2017 15 次提交
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由 Joel Stanley 提交于
Since Binutils 1a9ccd70f9a7[1] u-boot will not link targets that set CONFIG_SYS_TEXT_BASE=0 with the following error: LD u-boot arm-linux-gnueabi-ld.bfd: u-boot: Not enough room for program headers, try linking with -N arm-linux-gnueabi-ld.bfd: final link failed: Bad value The issue can be reproduced with the bad binutils and the rock2_defconfig target. This issue was also encountered by the powerpc kernel[2], with the fix being to pass --no-dynamic-linker for linkers newer than 2.26 when this flag was introduced. The option tells ld that the PIE or shared lib does not need loaded program headers. Ubuntu Zesty's Binutils 2.27.51.20161202 hits this error. [1] https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=commit;h=1a9ccd70f9a7 [2] https://git.kernel.org/cgit/linux/kernel/git/powerpc/linux.git/commit/?h=next&id=ff45000fcb56b5b0f1a14a865d3541746d838a0aSigned-off-by: NJoel Stanley <joel@jms.id.au> [AF: Apply to LDFLAGS_$(SPL_BIN) as well, suggested by Tom Rini] Signed-off-by: NAndreas Färber <afaerber@suse.de>
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由 Tom Rini 提交于
We disable this specific board as it does not link with the gcc-4.9.x that we use today in travis-ci. Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Andy Shevchenko 提交于
This simple PMU driver allows to tyrn power on and off for selected devices. In particularly Intel Tangier needs to power on SDHCI controllers in order to access to them during board initialization. In the future it might be expanded to cover other Intel MID platforms, that's why it's located under arch/x86/lib and called pmu.c. Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com> Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Felipe Balbi 提交于
Intel MID platforms have few microcontrollers inside SoC, one of them is so called System Controller Unit (SCU). Here is the driver to communicate with microcontroller. Signed-off-by: NVincent Tinelli <vincent.tinelli@intel.com> Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com> Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Andy Shevchenko 提交于
Add a specific serial driver for Intel MID platforms. It has special fractional divider which can be programmed via UART_PS, UART_MUL, and UART_DIV registers. The UART clock is calculated as UART clock = XTAL * UART_MUL / UART_DIV The baudrate is calculated as baud rate = UART clock / UART_PS / DLAB Initialize fractional divider correctly for Intel Edison platform. For backward compatibility we have to set initial DLAB value to 16 and speed to 115200 baud, where initial frequency is 29491200Hz, and XTAL frequency is 38.4MHz. Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
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由 Bin Meng 提交于
With recent changes, some x86-specific rom tests of binman fail to run. Fix it by adding missing filenames in corresponding entries. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Stefan Roese 提交于
Checking 'is_zimage' at this time will always fail and therefore booting a FIT style image will always lead to this error message: "## Kernel loading failed (missing x86 kernel setup) ..." This change now removes this check and booting of FIT images works just fine. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Stefan Roese 提交于
Now that we have added file names from Kconfig in x86 u-boot.dtsi, update binman to avoid using hard-coded names. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Stefan Roese 提交于
Since we now have the file names configurable via Kconfig for the flash descriptor and intel-me files, add these from Kconfig in the corresponding dts nodes. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Stefan Roese 提交于
This introduces two Kconfig options to enable board specific filenames for the Intel binary blobs to be used to generate the SPI flash image. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Bin Meng 提交于
At present there are only 8-bit and 32-bit read/write routines in the rtc uclass driver. This adds the 16-bit support. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Andy Shevchenko 提交于
There is option which is not used: CONFIG_ZBOOT_32 Remove it from default x86 config and from whitelist. Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Andrew F. Davis 提交于
Move the OPTEE load address to 0xbdb00000 in order to avoid overlap with the memory regions used in radio and RVC usecases. Signed-off-by: NAndrew F. Davis <afd@ti.com>
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由 Misael Lopez Cruz 提交于
Move the OPTEE load address to 0xbdb00000 in order to avoid overlap with the memory regions used in radio and RVC usecases. Signed-off-by: NMisael Lopez Cruz <misael.lopez@ti.com> Signed-off-by: NAndrew F. Davis <afd@ti.com>
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- 09 4月, 2017 8 次提交
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由 Andrew F. Davis 提交于
Enable SPL_USB_HOST_SUPPORT in the default defconfig to allow booting from USB peripherals. Unlike the non-HS boards, we already load SPL to a 0x4030_0000+ address, so no other changes are needed. Signed-off-by: NAndrew F. Davis <afd@ti.com>
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由 Andrew F. Davis 提交于
Enable CONFIG_SPL_USBETH_SUPPORT in the default defconfig to allow booting as a USB RNDIS peripheral. Signed-off-by: NAndrew F. Davis <afd@ti.com>
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由 Andrew F. Davis 提交于
Enable Eth/Net boot support in the default defconfig to allow network booting. Signed-off-by: NAndrew F. Davis <afd@ti.com>
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由 Andrew F. Davis 提交于
Additions have been made to the non-HS defconfig without the same being made to the HS defconfig, sync them. Signed-off-by: NAndrew F. Davis <afd@ti.com>
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由 Andrew F. Davis 提交于
Additions have been made to the non-HS defconfig without the same being made to the HS defconfig, sync them. Signed-off-by: NAndrew F. Davis <afd@ti.com>
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由 Andrew F. Davis 提交于
Additions have been made to the non-HS defconfig without the same being made to the HS defconfig, sync them. Signed-off-by: NAndrew F. Davis <afd@ti.com>
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由 Andrew F. Davis 提交于
Sync new additions to non-HS defconfig with HS defconfig. Also add SPL NAND support, this was disabled before due to size constraints, enable this now at the expense of the less used GPT partition support. Signed-off-by: NAndrew F. Davis <afd@ti.com>
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由 Andrew F. Davis 提交于
FIT support in the net boot case is much like the RAM boot case in that we load our image to "load_addr" and pass a dummy read function into "spl_load_simple_fit()". As the load address is no longer hard-coded to the final execution address, legacy image loading will require load_addr to be set correctly in the image header. Signed-off-by: NAndrew F. Davis <afd@ti.com>
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