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  1. 04 9月, 2018 4 次提交
    • Y
      dts: imx6ul: Update alias to support DM · 9e1e6f6f
      由 Ye Li 提交于 
      Add spi0 alias for qspi for enabling DM SPI.
Change usb alias for usbotg1 and usbotg2 for enabling DM USB
Signed-off-by: NYe Li <ye.li@nxp.com>
      9e1e6f6f
    • Y
      imx: imx7d-sdb: Add DM QSPI support · 3b823350
      由 Ye Li 提交于 
      On iMX7D SabreSD board, the QSPI has pins conflict with EPDC (default).
To use QSPI, users have to rework the board (de-populate R388-R391, R396-R399
populate R392-R395, R299, R300). So we add new DTS file and new defconfig
dedicated for QSPI.

Other changes to support the DM QSPI:
 - Add QSPI node and alias spi0.
 - Modify spi4 (spi-gpio) node and add alias spi5 for it to avoid req
   conflict
 - Add EPDC node in imx7d.dtsi and disable it in imx7d-sdb-qspi.dts to
   align with kernel and also present the conflict.
 - Add -u-boot.dtsi to modify compatible string of mx25l51245g@0 to
   "spi-flash"
 - Remove iomux settings of qspi in board codes which is not needed
   for DM driver.
Signed-off-by: NYe Li <ye.li@nxp.com>
      3b823350
    • Y
      imx: imx6sx-sabreauto: convert to use DM QSPI driver · 0925ee21
      由 Ye Li 提交于 
      To support DM QSPI driver:
 - Add -u-boot.dtsi to modify n25q256a@0 and n25q256a@1 compatible string
   to "spi-flash" and add "num-cs" property.
 - Enable DM SPI and DM SPI FLASH configurations
 - Remove iomux settings of qspi1 in board codes which is not needed
   for DM driver.
Signed-off-by: NYe Li <ye.li@nxp.com>
      0925ee21
    • Y
      imx: imx6sx-sdb: Enable DM QSPI driver · 536c5c7a
      由 Ye Li 提交于 
      To support DM QSPI driver
 - Add spi0 and spi1 alias for qspi1 and qspi2.
 - Add -u-boot.dtsi to modify n25q256a@0 and n25q256a@1 compatible string
   to "spi-flash" and add "num-cs" property.
 - Enable DM SPI/QSPI relavent configurations
 - Remove iomux settings of qspi2 in board codes which is not needed
   for DM driver.
 - Add sf default settings. So running "sf probe" can detect the flash
Signed-off-by: NYe Li <ye.li@nxp.com>
      536c5c7a
  3. 27 8月, 2018 2 次提交
  5. 25 8月, 2018 18 次提交
  7. 24 8月, 2018 10 次提交
    • M
      ARM: dts: socfpga: Add missing NAND reset · a029f540
      由 Marek Vasut 提交于 
      The NAND reset is missing from DT, so the reset manager cannot unreset the NAND.
Add the missing DT reset entry.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
      a029f540
    • M
      ARM: dts: socfpga: Drop ad-hoc UART clock frequency encoding from DT · b67f8014
      由 Marek Vasut 提交于 
      The UART clock frequency can be obtained from the clock framework by the
ns16550 driver, so drop this redundant DT node.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
      b67f8014
    • M
      ARM: socfpga: Convert Arria10 to timer framework · 331c3722
      由 Marek Vasut 提交于 
      Switch the Arria10 from ad-hoc hardcoded timer to timer framework
and the DW APB timer driver. This allows the A10 to extract timer
information, like timer rate, from clock framework and thus DT
instead of having it hardcoded in U-Boot configuration files.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
      331c3722
    • M
      ARM: dts: socfpga: Flag timer clock as pre-reloc · cca9af63
      由 Marek Vasut 提交于 
      Flag timer clock as DM pre-reloc, so that a timer driver can be used and
it can extract information about it's clock rate using the clock framework.
This patch also moves some of the pre-reloc flags into the core dtsi file,
this is because the timer is not board specific, but rather is used on all
boards.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
      cca9af63
    • M
      timer: dw-apb: Add Designware APB timer driver · 66011a08
      由 Marek Vasut 提交于 
      Add timer driver for the Designware APB Timer IP. This is present
for example on the Altera SoCFPGA chips.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
      66011a08
    • M
      ARM: socfpga: Reorder Arria10 SPL · 0b8f6378
      由 Marek Vasut 提交于 
      The Arria10 SPL is a complete mess of calls to functions which are
called in the wrong context and it is surprise it works at all. This
patch tries to clean that mess up by shuffling the function calls
around and moving the calls into the correct context. Due to the
delicate nature of the reordering, this is done in one huge patch.

The following changes happen in this patch:
- Security policy init and NIC301 happens first in board_init_f()
- The clock init happens very early in board_init_f() in SPL only
- arch_early_init_r() only registers the FPGA, just like on Gen5
- arch_early_init_r() is never called from any _f() function
- Dedicated FPGA pins are inited in board_init_f() as on Gen5
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
      0b8f6378
    • L
      arm: socfpga: stratix10: Fix mailbox urgent command with urgent register · 8497cb9b
      由 Ley Foon Tan 提交于 
      According to mailbox spec, software should send urgent command with
urgent register instead of COUT location. This patch write urgent
command index to urgent register.
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>
      8497cb9b
    • L
      arm: socfpga: stratix10: Enable EMAC to FPGA bridge based on handoff · db3b5e98
      由 Ley Foon Tan 提交于 
      Code checking and setting EMAC use fpga is in
populate_sysmgr_fpgaintf_module(). So, call to sysmgr_pinmux_init()
instead of populate_sysmgr_pinmux().
In sysmgr_pinmux_init(), it will call to both populate_sysmgr_pinmux()
and populate_sysmgr_fpgaintf_module().
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>
      db3b5e98
    • T
      Merge git://git.denx.de/u-boot-fsl-qoriq · 3b1c0d89
      由 Tom Rini 提交于
      3b1c0d89
    • S
      Partially revert "efi_loader: Rename sections to allow for implicit data" · 7bf07cf8
      由 Simon Glass 提交于 
      This partially reverts commit 7e21fbca.

That change broke sandbox EFI support for unknown reasons. It also changes
sandbox to use--gc-sections which we don't want.

For now I am just reverting the sandbox portion as presumably this change
is safe on other architectures.

Fixes: 7e21fbca (efi_loader: Rename sections to allow for implicit data)
Signed-off-by: NSimon Glass <sjg@chromium.org>
      7bf07cf8
  9. 23 8月, 2018 6 次提交