1. 16 7月, 2019 1 次提交
  2. 11 7月, 2019 1 次提交
  3. 13 6月, 2019 1 次提交
  4. 24 5月, 2019 1 次提交
  5. 08 5月, 2019 3 次提交
  6. 05 5月, 2019 1 次提交
    • V
      arch: armv8: Provide a way to disable cache maintenance ops · add49671
      Vignesh Raghavendra 提交于
      On AM654 SoC(arm64) which is IO coherent and has L3 Cache, cache
      maintenance operations being done to support non-coherent platforms
      causes issues.
      
      For example, here is how U-Boot prepares/handles a buffer to receive
      data from a device (DMA Write). This may vary slightly depending on the
      driver framework:
      
      	Start DMA to write to destination buffer
      	Wait for DMA to be done (dma_receive()/dma_memcpy())
      	Invalidate destination buffer (invalidate_dcache_range())
      	Read from destination buffer
      
      The invalidate after the DMA is needed in order to read latest data from
      memory that’s updated by DMA write. Also, in case random prefetch has
      pulled in buffer data during the “wait for DMA” before the DMA has
      written to it. This works well for non-coherent architectures.
      
      In case of coherent architecture with L3 cache, DMA write would directly
      update L3 cache contents (assuming cacheline is present in L3) without
      updating the DDR memory. So invalidate after “wait for DMA” in above
      sequence would discard latest data and read will cause stale data to be
      fetched from DDR. Therefore invalidate after “wait for DMA” is not
      always correct on coherent architecture.
      
      Therefore, provide a Kconfig option to disable cache maintenance ops on
      coherent architectures. This has added benefit of improving the
      performance of DMA transfers as we no longer need to invalidate/flush
      individual cache lines(especially for buffer thats several KBs in size).
      
      In order to facilitate use of same Kconfig across different
      architecture, I have added the symbol to top level arch/Kconfig file.
      Patch currently disables cache maintenance ops for arm64 only.
      flush_dcache_all() and invalidate_dcache_all() are exclusively used
      during enabling/disabling dcache and hence are not disabled.
      Signed-off-by: NVignesh Raghavendra <vigneshr@ti.com>
      add49671
  7. 27 2月, 2019 1 次提交
  8. 20 2月, 2019 1 次提交
  9. 14 12月, 2018 1 次提交
    • S
      dm: sound: Create an option to use driver model for sound · 2a049572
      Simon Glass 提交于
      The U-Boot sound system provides basic support for beeping. At present it
      does not use driver model, but it needs to be converted. Add an option to
      enable driver model for sound. For now it is not connected to anything.
      Future work will add drivers which use this option. It will then be
      removed once everything is converted.
      Signed-off-by: NSimon Glass <sjg@chromium.org>
      2a049572
  10. 26 11月, 2018 1 次提交
  11. 15 11月, 2018 2 次提交
  12. 08 10月, 2018 1 次提交
  13. 07 10月, 2018 1 次提交
  14. 03 10月, 2018 3 次提交
  15. 30 9月, 2018 1 次提交
  16. 18 9月, 2018 1 次提交
  17. 30 7月, 2018 2 次提交
  18. 20 7月, 2018 1 次提交
  19. 28 4月, 2018 1 次提交
    • A
      Convert CONFIG_SPI to Kconfig · f1b1f770
      Adam Ford 提交于
      This converts the following to Kconfig:
         CONFIG_SPI
      
      This partly involves updating code that assumes that CONFIG_SPI implies
      things that are specific to the MPC8xx SPI driver.  For now, just update
      the CONFIG tests.  This also involves reworking the default for
      CONFIG_SYS_DEF_EEPROM_ADDR so that we don't set it when we cannot make a
      reasonable default, as it does not cause any compile failures.
      Signed-off-by: NAdam Ford <aford173@gmail.com>
      Signed-off-by: NTom Rini <trini@konsulko.com>
      f1b1f770
  20. 09 2月, 2018 1 次提交
  21. 31 1月, 2018 1 次提交
  22. 12 1月, 2018 1 次提交
  23. 08 9月, 2017 2 次提交
  24. 24 8月, 2017 1 次提交
  25. 12 8月, 2017 2 次提交
  26. 01 8月, 2017 7 次提交