As experienced on lwmon5, on some boards the POST memory test can
corrupt the global data buffer (bd). This patch fixes this issue
by checking and limiting this area.
Signed-off-by: NYuri Tikhonov <yur@emcraft.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Since this RTC POST test is taking quite a while to complete
it's only initiated upon special keypress same as the complete
memory POST.
Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NStefan Roese <sr@denx.de>

This patch adds support for the 2nd EEPROM (AT24C128) on the lwmon5
board. Now the "eeprom" command can be used to read/write from/to this
device. Additionally a new command was added "eepromwp" to en-/disable
the write-protect of this 2nd EEPROM.

The 1st EEPROM is not affected by this write-protect command.
Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NStefan Roese <sr@denx.de>

This patch adds support for the matrix keyboard on the lwmon5 board.
Since the implementation in the dsPCI is kind of compatible with the
"old" lwmon board, most of the code is copied from the lwmon
board directory.
Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NWolfgang Denk <wd@denx.de>

platforms wishing to display RAM diagnostics in addition to size,
can do so, on one line, in their own board_add_ram_info()
implementation.

this consequently eliminates CONFIG_ADD_RAM_INFO.

Thanks to Stefan for the hint.
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

This patch has been sent on:
- 6 Jun 2007

Many users of PCI config read routines tend to ignore the function
ret value, and are only concerned about the contents of *val. Based
on this, pci_hose_read_config_{byte,word}_via_dword should initialize
the *val on dword read error.

Without this fix, for example, we'll go on scanning bus with vendor or
header_type uninitialized. This brings many unnecessary config trials.
Signed-off-by: NShinya Kuribayashi <shinya.kuribayashi@necel.com>

Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NTsiChungLiew <Tsi-Chung.Liew@freescale.com>

introduced in the implement board_add_ram_info patch as I was cleaning out the
magic numbers.  sorry.
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

includes build fixes.
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

add board_add_ram_info, to make memory diagnostic output more
consistent. u-boot banner output now looks like:

DRAM:  256 MB (DDR1, 64-bit, ECC on)

and for boards with SDRAM on the local bus, a line such as this is
added:

SDRAM: 64 MB (local bus)

also replaced some magic numbers with their equivalent define names.
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

The patch split the PIB init code from pci.c to a single file board/freescale/common/pq-mds-pib.c
And add Qoc3 ATM card support for MPC8360EMDS and MPC832XEMDS board.

Signed-off-by Tony Li <tony.li@freescale.com>

Signed-off-by: NTsiChungLiew <Tsi-Chung.Liew@freescale.com>

Signed-off-by: NTsiChungLiew <Tsi-Chung.Liew@freescale.com>

Signed-off-by: NTsiChungLiew <Tsi-Chung.Liew@freescale.com>

Signed-off-by: NTsiChungLiew <Tsi-Chung.Liew@freescale.com>

Signed-off-by: NTsiChungLiew <Tsi-Chung.Liew@freescale.com>

Signed-off-by: NTsiChungLiew <Tsi-Chung.Liew@freescale.com>

Signed-off-by: NTsiChungLiew <Tsi-Chung.Liew@freescale.com>

Signed-off-by: NTsiChungLiew <Tsi-Chung.Liew@freescale.com>

Signed-off-by: NTsiChungLiew <Tsi-Chung.Liew@freescale.com>

Signed-off-by: NTsiChungLiew <Tsi-Chung.Liew@freescale.com>

Signed-off-by: NTsiChungLiew <Tsi-Chung.Liew@freescale.com>

Signed-off-by: NTsiChungLiew <Tsi-Chung.Liew@freescale.com>

Signed-off-by: NTsiChungLiew <Tsi-Chung.Liew@freescale.com>

Signed-off-by: NTsiChungLiew <Tsi-Chung.Liew@freescale.com>

The 85xx code now relies on CONFIG_HAS_ETH0 to determine whether
to update TSEC1's device-tree node, so we need to add it
to all the boards with TSECs.  Do this for 83xx and 86xx, too,
since they will eventually do something similar.
Signed-off-by: NAndy Fleming <afleming@freescale.com>

The PCIe bus that the ULI M1575 is connected to has no possible way of
needing more than the fixed amount of IO & Memory space needed by the ULI.

So make it use far less IO & memory space and have it use the shared LAW.  This
free's up a LAW for PCIe1 IO space.  Also reduce the amount of IO space needed
by each bus.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>