This patch disables the 44x d-cache on 'usb start' and
reenables it on 'usb stop'. This should be seen as a
temporary fix until the generic usb-ohci driver can
life with d-cache enabled.
Signed-off-by: NMatthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: NStefan Roese <sr@denx.de>

This patch removes some redundant code and decrements the end
address of cache flush and invalidate by 1.
Signed-off-by: NMatthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NStefan Roese <sr@denx.de>

Most 4xx PPC capable of using an I2C bootrom for bootstrap setting
already print a line with the information which I2C bootrom is
used for bootstrap configuration. So we don't need this extra line
with "I2C boot EEPROM en-/dis-abled".

This patch also has a little code cleanup integrated.
Signed-off-by: NStefan Roese <sr@denx.de>

Now not max 3 lines but 2 lines are printed per PCIe port.
Signed-off-by: NStefan Roese <sr@denx.de>

This patch adds NAND booting support for the AMCC 405EX(r) eval boards.
Again, only one image supports both targets.
Signed-off-by: NStefan Roese <sr@denx.de>

Since the cache handling functions were moved from start.S into cache.S
the acadia NAND booting Makfile needs to be adapted accordingly.
Signed-off-by: NStefan Roese <sr@denx.de>

This patch adds the CONFIG_4xx_DCACHE options to some SDRAM init files
and to the Sequoia TLB init code. Now the cache can be enabled on 44x
boards by defining CONFIG_4xx_DCACHE in the board config file. This
option will disappear, when more boards use is successfully and no
more known problems exist.

This is tested successfully on Sequoia and Katmai. The only problem that
needs to be fixed is, that USB is not working on Sequoia right now, since
it will need some cache handling code too, similar to the 4xx EMAC driver.
Signed-off-by: NStefan Roese <sr@denx.de>

Now with caches enabled (i- and d-cache) on 44x, we need a chance to
disable the cache for the CPU POST tests, since these tests consist
of self modifying code. This is done via the new change_tlb() function.
Signed-off-by: NStefan Roese <sr@denx.de>

This patch enables the 4xx EMAC POST driver to work too, when dcache is
enabled.
Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NStefan Roese <sr@denx.de>

This patch enables the 4xx EMAC driver to work too, when dcache is
enabled.
Signed-off-by: NStefan Roese <sr@denx.de>

This function is used to either turn cache on or off in a specific
memory area.
Signed-off-by: NStefan Roese <sr@denx.de>

All 4xx board config files don't need the cache definitions anymore.
These are now defined in common headers.
Signed-off-by: NStefan Roese <sr@denx.de>

New cache handling functions added and all existing functions
moved from start.S into seperate cache.S.
Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NStefan Roese <sr@denx.de>

I lately noticed, that newer 4xx board with GBit support sometimes don't
finish link autonegotiation in 4 seconds. Changing this timeout to 5
seconds seems fine here.
Signed-off-by: NStefan Roese <sr@denx.de>

This patch changes all in32/out32 calls to use the recommended in_be32/
out_be32 macros instead.
Signed-off-by: NStefan Roese <sr@denx.de>

The POST ethernet test needed to be changed to dynamically determine
the count of ethernet devices. This code is cloned from the 4xx
ethernet driver.
Signed-off-by: NStefan Roese <sr@denx.de>

We now use a value in the gd (global data) structure for the UART input
frequency, since the PPC4xx_SYS_INFO struct is always rewritten completely
in get_sys_info().
Signed-off-by: NStefan Roese <sr@denx.de>

The Haleakala is nearly identical with the Kilauea eval board. The only
difference is that the 405EXr only supports one EMAC and one PCIe
interface. This patch adds support for the Haleakala board by using
the identical image for Kilauea and Haleakala. The distinction is done
by comparing the PVR.
Signed-off-by: NStefan Roese <sr@denx.de>

This patch also adds a note to the fixed DDR setup for Bamboo NAND booting:

Note:
As found out by Eugene O'Brien <eugene.obrien@advantechamt.com>, the fixed
DDR setup has problems (U-Boot crashes randomly upon TFTP), when the DIMM
modules are still plugged in. So it is recommended to remove the DIMM
modules while using the NAND booting code with the fixed SDRAM setup!
Signed-off-by: NEugene O'Brien <eugene.obrien@advantechamt.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NStefan Roese <sr@denx.de>

Change 4xx_uart.c:

- Use in_8/out_8 macros instead of in8/out8
- No need for UART_BASE marco anymore, now really handled via function
  parameter
- serial_init_common() introduced
- Further coding style cleanup
Signed-off-by: NStefan Roese <sr@denx.de>

Change all linker scripts to reference the changed driver name iop480_uart.o.
Signed-off-by: NStefan Roese <sr@denx.de>

Change all linker scripts to reference the changed driver name 4xx_uart.o.

Note: In most cased all these explicit referencing of these object files
in the linker scripts is not neccessary. Only for manually embedded
environment into the U-Boot image, which is not done is most cases.
Signed-off-by: NStefan Roese <sr@denx.de>

This patch starts the rework of the PPC4xx serial driver. First we split
the file into two seperate files, one 4xx_uart.c with the 405/440 UART
handling code and the other one iop480_uart.c with the UART code for the
PLX-Tech IOP480 PPC (PPC403 based).
Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NStefan Roese <sr@denx.de>

This value is needed later for the device tree configuration of
the uart clock.
Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NStefan Roese <sr@denx.de>

This patch adds support for the Xicor/Intersil X1205 RTC used on the
AMCC Makalu eval board. This driver is basically cloned from the Linux
driver version (2.6.23).

This patch also introduces the Linux bcd.h header for the BCD2BIN/
BIN2BCD conversions. In the future some of the other U-Boot RTC driver
should be converted to also use this header instead of implementing
their own local copy of these functions/macros.
Signed-off-by: NStefan Roese <sr@denx.de>

This patch moves some common 4xx macros and the PPC405_SYS_INFO/
PPC440_SYS_INFO structure into the common ppc4xx.h header.

Lot's of other macros are good candidates to be consolidated this way
in the future.
Signed-off-by: NStefan Roese <sr@denx.de>

The size was initilized wrong. Instead of 256MB, the DDR2 controller
was setup to 512MB. Now the correct values is used.

This patch also does a little cleanup and adds a comment here.
Signed-off-by: NStefan Roese <sr@denx.de>

CONFIG_BOOKE must be defined for PPC440 processors so that the proper SPR
number is used to access system registers.
Signed-off-by: NEugene O'Brien <eugene.obrien@advantechamt.com>
Signed-off-by: NStefan Roese <sr@denx.de>

On Yucca & Katmai, the inbound memory map pointed to 0x4.0000.0000, which
is the internal SRAM. Since I now ported and tested this endpoint mode
on Kilauea successfully to map to 0 (SDRAM), I also changed this for
Katmai.

Yucca will stay at internal SRAM for now. Not sure if somebody relies on
this setup.
Signed-off-by: NStefan Roese <sr@denx.de>

This patch adds endpoint support for the AMCC Kilauea eval board. It can
be tested by connecting a reworked PCIe cable (only 1x lane singles
connected) to another root-complex.

In this test setup, a 64MB inbound window is configured at BAR0 which maps
to 0 on the PLB side. So accessing this BAR0 from the root-complex will
access the first 64MB of the SDRAM on the PPC side.
Signed-off-by: NStefan Roese <sr@denx.de>

This patch adds support for dynamic configuration of PCIe ports for the
AMCC PPC4xx boards equipped with PCIe interfaces. These are the PPC440SPe
boards Yucca & Katmai and the 405EX board Kilauea.

This dynamic configuration is done via the "pcie_mode" environement
variable. This variable can be set to "EP" or "RP" for endpoint or
rootpoint mode. Multiple values can be joined via the ":" delimiter.
Here an example:

pcie_mode=RP:EP:EP

This way, PCIe port 0 will be configured as rootpoint, PCIe port 1 and 2
as endpoint.

Per default Yucca will be configured as:
pcie_mode=RP:EP:EP

Per default Katmai will be configured as:
pcie_mode=RP:RP:REP

Per default Kilauea will be configured as:
pcie_mode=RP:RP
Signed-off-by: NTirumala R Marri <tmarri@amcc.com>
Signed-off-by: NStefan Roese <sr@denx.de>

This patch enables the fdt support on the AMCC Kilauea eval board.
Additionally now EBC ranges fdt fixup is included to support NOR
FLASH mapping via the Linux physmap_of driver.

This Kilauea port now support booting arch/ppc and arch/powerpc
Linux kernels. The default environment "net_nfs" is for arch/ppc
and "net_nfs_fdt" is for arch/powerpc. In the long run, arch/ppc
support will be removed.
Signed-off-by: NStefan Roese <sr@denx.de>