Some erratum patch might need it to program registers.
Signed-off-by: NRan Wang <ran.wang_1@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

EC1 and EC2 are RGMII interface on ls1088aqds platform.
This patch add support of RGMII with PHY and MDIO
Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: NAmrita Kumari <amrita.kumari@nxp.com>
Signed-off-by: NAshish Kumar <ashish.kumar@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

This patch adds support for RGMII protocol

NXP's LDPAA2 support RGMII protocol. LS1088A is the
first Soc supporting both RGMII and SGMII.
Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: NAmrita Kumari <amrita.kumari@nxp.com>
Signed-off-by: NAshish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

This patch add support of LS1088AQDS platform.

The LS1088A QorIQTM Development System (QDS) is a high-performance
computing, evaluation, and development platform that supports the
LS1088A QorIQ Architecture processor.
Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: NShaohui Xie <Shaohui.Xie@nxp.com>
Signed-off-by: NAshish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

LS1088A is an ARMv8 implementation. The LS1088ARDB is an evaluatoin
platform that supports the LS1088A family SoCs. This patch add basic
support of the platform.
Signed-off-by: NAlison Wang <alison.wang@nxp.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: NAshish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: NRaghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: NShaohui Xie <Shaohui.Xie@nxp.com>
[YS: Disabled NAND in board header file]
Reviewed-by: NYork Sun <york.sun@nxp.com>

WIP: disable NAND for LS1088ARDB

LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.
Signed-off-by: NAlison Wang <alison.wang@nxp.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: NAshish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: NRaghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: NShaohui Xie <Shaohui.Xie@nxp.com>
[YS: Revised commit message]
Reviewed-by: NYork Sun <york.sun@nxp.com>

For QSPI and IFC addresses execution shouldn't be allowed
when u-boot running from DDR. Revise the MMU final table
to enforce execute-never bits.
Signed-off-by: NSuresh Gupta <suresh.gupta@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

According current code base, CONFIG_LS1012A should be
CONFIG_ARCH_LS1012A, or function fsl_fdt_disable(blob) will be
wrongly called to disable all dwc3 USB nodes on LS1012A, which
cause Linux USB function stop working at all.
Signed-off-by: NRan Wang <ran.wang_1@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Update MC address calculation as per MC design requirement of address
as least significant 512MB address of MC private allocated memory,
i.e. address should point to end address masked with 512MB offset in
private DRAM block.
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: NAshish Kumar <ashish.kumar@nxp.com>
[YS: reformatted commit message]
Reviewed-by: NYork Sun <york.sun@nxp.com>

LS2080 family has CCN-504 cache coherent interconnet. Other SoCs
in LSCH3 family may have differnt interconnect.
Signed-off-by: NAshish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
[YS: revised commit message]
Reviewed-by: NYork Sun <york.sun@nxp.com>

If CONFIG_SPL_OS_BOOT is enabled, boot OS if kernel image is found
in FIT structure.
Signed-off-by: NYork Sun <york.sun@nxp.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

SPL supports U-Boot image in FIT format which has data outside of
FIT structure. This adds support for embedded data for normal FIT
images.
Signed-off-by: NYork Sun <york.sun@nxp.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Add Kconfig option SPL_GZIP and SPL_ZLIB to enable gunzip support for
SPL boot, eg. falcon boot compressed kernel image.
Signed-off-by: NYork Sun <york.sun@nxp.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Fix warning "cast from pointer to integer of different size".
Signed-off-by: NYork Sun <york.sun@nxp.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

The image size should be added to the initial pbl command, not bit
"ORed".
Signed-off-by: NYork Sun <york.sun@nxp.com>

Signed-off-by: NUdit Agarwal <udit.agarwal@nxp.com>
[YS: dropped redundant commit message]
Reviewed-by: NYork Sun <york.sun@nxp.com>

Adds header address for PPA to be validated during ESBC phase for
ARCH_LS2088 and QSPI_BOOT. Moves sec_init prior to ppa_init(). It
must be initialized before the PPA.
Signed-off-by: NUdit Agarwal <udit.agarwal@nxp.com>
[YS: revised commit message]
Reviewed-by: NYork Sun <york.sun@nxp.com>

Unify memory map for Layerscape based platforms. This patch includes
changes in bootscript, bootscript header and PPA header addresses
change as per unified memory map.
Signed-off-by: NSumit Garg <sumit.garg@nxp.com>
Tested-by: NVinitha Pillai <vinitha.pillai@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

QE_IRAM_READY should be set only after successfully uploading the
firmware.
Signed-off-by: NZhao Qiang <qiang.zhao@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

CoreLink Cache Coherent Interconnect (CCI) provides full cache
coherency between two clusters of multi-core CPUs and I/O coherency
for devices and I/O masters.

This patch add new config option SYS_FSL_HAS_CCI400 and moves
existing register space definaton of CCI-400 bus to fsl_immap to be
shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET
in Kconfig.
Signed-off-by: NAshish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
[YS: revised commit message, squashed patches for armv8 and armv7]
Reviewed-by: NYork Sun <york.sun@nxp.com>

At present the IDE device number is initialized to -1, which means
we cannot type "ide read" command before setting the device number
via "ide device #".

For convenience, let's set the first device as the default one.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

When there is no CDROM inserted, the block size is zero hence there
is no need to create a BLK device for it.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

This converts the IDE driver to driver model so that block read and
write are fully functional.

Fixes: b7c6baef ("x86: Convert MMC to driver model")
Reported-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Tested-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

So far these are using magic numbers. Replace them with macros.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

This board does dwc3 gadget, not host, so we cannot have host support or
we will fail to link.
Signed-off-by: NTom Rini <trini@konsulko.com>

The underlying implementation for ENV_AES has security complications and
is not recommended for use.  Please see CVE-2017-3225 and CVE-2017-3226
for more details.  Mark this as deprecated now and delete this in the
medium term if no one comes forward to re-work the support.
Signed-off-by: NTom Rini <trini@konsulko.com>

A number of the config options for USB networking have been migrated to
Kconfig. Update README.usb to reflect this.
Signed-off-by: NChris Packham <judge.packham@gmail.com>

This migrates ASIX, ASIX88179, MCS7830, RTL8152 and SMSC95XX to Kconfig.
Update defconfigs.
Signed-off-by: NChris Packham <judge.packham@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

CONFIG_USB_HOST_ETHER is the framework that the drivers are dependent on
USB_HOST_ETHER. Use this as a menu and move the existing LAN75XX and
LAN78XX options under new menu. Finally update the defconfigs that need
CONFIG_USB_HOST_ETHER.
Signed-off-by: NChris Packham <judge.packham@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

This is not a valid option. Drop it.
Signed-off-by: NChris Packham <judge.packham@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

This is not a valid option. Drop it.
Signed-off-by: NChris Packham <judge.packham@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

The correct name is 'gd->fdt_blob', not 'gd->blob'.
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Simon Glass <sjg@chromium.org>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Rsync all defconfig files using moveconfig.py
Signed-off-by: NTom Rini <trini@konsulko.com>

With Makefiles testing for $(SPL_TPL_)SYSRESET, we need SPL_SYSRESET
for do_reset() in SPL for Rockchip SoCs.

References: 87c16d49 "drivers: spl: consistently use the $(SPL_TPL_) macro"
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Acked-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

syscon id table need a dummy member as NULL ending, or else system
will panic while try to match a compatible in this table as a list.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Acked-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

Disable CONFIG_ARCH_FIXUP_FDT_MEMORY to prevent U-Boot from modifying
the memory {} nodes in the DT passed to the Linux kernel. The R8A779x
DT contains multiple memory {} nodes, while U-Boot only modifies the
first one and stuffs all the memory entries into it, which is wrong.
Disabling CONFIG_ARCH_FIXUP_FDT_MEMORY is the least intrusive way to
fix the issue this close to the release, while the real fix is to
extend the fdt_fixup_memory_banks() to handle multiple memory nodes
in DT.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

On RCar M3 and on RCar H3 newer than and not including ES1.0, the SD clock
must be divided by 4 rather than 2 because a hardware workaround present
only in the H3 ES1.0 has been removed from these chips. U-Boot currently
only supports M3 and H3 ES 2.0 and newer, so configure the SD pre-divider
to 4 to prevent SD instability.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

%s/Desriptor/Descriptor/g
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Signed-off-by: NMadalin Bucur <madalin.bucur@nxp.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Acked-by: NYork Sun <york.sun@nxp.com>