Add DDR2 support to Gen5 DRAM driver. As the DDR2 macro names generated
by Quartus are named differently than the DDR3 ones, use anon unions to
store them in the same structures, without growing their size.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

Add optional support for fetching watchdog clock rate from DT
and ungating reset via reset framework. This is optional as not
all platforms using DW WDT support the clock and reset frameworks
yet.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Philipp Tomisch <philipp.tomisch@theobroma-systems.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # roc-rk3399-pc

Convert the designware watchdog timer driver to DM and add DT probing
support. Perform minor coding style clean up, like drop superfluous
braces. These ought to be no functional change.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Philipp Tomisch <philipp.tomisch@theobroma-systems.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # roc-rk3399-pc

Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig and update the headers
accordingly, no functional change. The S10 enables the WDT only in
SPL, but does not enable it in U-Boot itself, hence disable it in
the config again.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Philipp Tomisch <philipp.tomisch@theobroma-systems.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>

This particular chunk of code was not updated, likely due to the order
in which the patches were posted and applied. Fix this missing part.

Fixes: bb25aca1 ("arm: socfpga: Convert reset manager from struct to defines")
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>

In Cyclone 5 SoC platform, the first USB probing is failed but second
probing is success. DWC2 USB driver read gsnpsid register right after
de-assert reset, but controller is not ready yet and it returns gsnpsid 0.
Polling reset status after de-assert reset to solve the issue.

Retry with this fix more than 10 times without issue.
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>

- DFU and Cadence USB 3 fixes

Add a new option to enable the DROP_FFS flag when flashing UBI images to
NAND in order to drop trailing all-0xff pages.

This is similar to the existing FASTBOOT_FLASH_NAND_TRIMFFS option.
Signed-off-by: NGuillermo Rodriguez <guille.rodriguez@gmail.com>
Cc: Lukasz Majewski <lukma@denx.de>

Invalidate dcache line before accessing Setup Packet contents. Otherwise
driver will see stale content on non coherent architecture.
Signed-off-by: NVignesh Raghavendra <vigneshr@ti.com>

- Support redundant boot for rk3399
- Support binman for rockchip platform
- Update ram driver and add ddr4 support for rk3328

UniPhier SoC updates for v2020.04 (2nd)

Denali NAND driver changes:
 - Set up more registers in denali-spl for SOCFPGA
 - Make clocks optional
 - Do not assert reset signals in the remove hook
 - associate SPARE_AREA_SKIP_BYTES with DT compatible
 - switch to UCLASS_MTD

UniPhier platform changes:
 - fix a bug in dram_init()
 - specify loadaddr for "source" command

If the "source" command is not given the address, it uses
CONFIG_SYS_LOAD_ADDR, which is compile-time determined.

Using the "loadaddr" environment variable is handier because it is
relocated according to the memory base when CONFIG_POSITION_INDEPENDENT
is enabled.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

gd->ram_base is not set at all if the end address of the DRAM ch0
exceeds the 4GB limit.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

UCLASS_MTD is a better fit for NAND drivers.

Make NAND_DENALI_DT depend on DM_MTD, which is needed to compile
drivers/mtd/mtd-uclass.c

Also, make ARCH_UNIPHIER select DM_MTD because all the defconfig
of this platform enables NAND_DENALI_DT.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: NMiquel Raynal <miquel.raynal@bootlin.com>

Now that the reset controlling of the Denali NAND driver (denali_dt.c)
works for this platform, remove the adhoc reset deassert code.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Currently, the denali NAND driver in U-Boot configures the
SPARE_AREA_SKIP_BYTES based on the CONFIG option.

Recently, Linux kernel merged a patch that associates the proper
value for this register with the DT compatible string.

Do likewise in U-Boot too.

The denali_spl.c still uses CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

When the reset signal is de-asserted, the HW-controlled bootstrap
starts running unless it is disabled in the SoC integration.
It issues some commands to detect a NAND chip, and sets up registers
automatically. Until this process finishes, software should avoid
any register access.

Without this delay function, some of UniPhier boards hangs up while
executing nand_scan_ident(). (denali_read_byte() is blocked)
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The Denali NAND driver in mainline Linux currently cannot deassert the
reset. The upcoming Linux 5.6 will support the reset controlling, and
also set up SPARE_AREA_SKIP_BYTES correctly. So, the Denali driver in
the future kernel will work without relying on any bootloader or firmware.
However, we still need to take care of stable kernel versions for a while.
U-boot should not assert the reset of this controller.

Fixes: ed784ac3 ("mtd: rawnand: denali: add reset handling")
Signed-off-by: NMarek Vasut <marex@denx.de>
[yamada.masahiro: reword the commit description]
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The "nand_x" and "ecc" clocks are currently optional. Make the core
clock optional in the same way. This will allow platforms with no clock
driver support to use this driver.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Tested-by: Marek Vasut <marex@denx.de> # On SoCFPGA Arria V

On Altera SoCFPGA, upon either cold-boot or power-on reset, the
Denali NAND IP is initialized by the BootROM ; upon warm-reset,
the Denali NAND IP is NOT initialized by BootROM. In fact, upon
warm-reset, the SoCFPGA BootROM checks whether the SPL image in
on-chip RAM is valid and if so, completely skips re-loading the
SPL from the boot media.

This does sometimes lead to problems where the software left
the boot media in inconsistent state before warm-reset, and
because the BootROM does not reset the boot media, the boot
media is left in this inconsistent state, often until another
component attempts to access the boot media and fails with an
difficult to debug failure. To mitigate this problem, the SPL
on Altera SoCFPGA always resets all the IPs on the SoC early
on boot.

This results in a couple of register values, pre-programmed by
the BootROM, to be lost during this reset. To restore correct
operation of the IP on SoCFPGA, these values must be programmed
back into the controller by the driver. Note that on other SoCs
which do not use the HW-controlled bootstrap, more registers
may have to be programmed.

This also aligns the SPL behavior with the full Denali NAND
driver, which sets these values in denali_hw_init().
Signed-off-by: NMarek Vasut <marex@denx.de>
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

- Assorted minor fixes
- Revert 6dcb8ba4 from upstream libfdt to restore boot-time speed on
  many platforms.

Same as the upstream fix for building dtc with gcc 10.
Signed-off-by: NPeter Robinson <pbrobinson@gmail.com>

Since commit e1910d93 ("doc: driver-model: Convert MIGRATION.txt to
reST") MIGRATION.txt has been converted to migration.rst, so update
the Makefile references accordingly.

Fixes: e1910d93 ("doc: driver-model: Convert MIGRATION.txt to reST")
Signed-off-by: NFabio Estevam <festevam@gmail.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Signed-off-by: NFlavio Suligoi <f.suligoi@asem.it>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Signed-off-by: NFlavio Suligoi <f.suligoi@asem.it>

Signed-off-by: NJorge Ramirez-Ortiz <jorge@foundries.io>

Signed-off-by: NJorge Ramirez-Ortiz <jorge@foundries.io>

In upstream libfdt, 6dcb8ba4 "libfdt: Add helpers for accessing
unaligned words" introduced changes to support unaligned reads for ARM
platforms and 11738cf01f15 "libfdt: Don't use memcpy to handle unaligned
reads on ARM" improved the performance of these helpers.

In practice however, this only occurs when the user has forced the
device tree to be placed in memory in a non-aligned way, which in turn
violates both our rules and the Linux Kernel rules for how things must
reside in memory to function.

This "in practice" part is important as handling these other cases adds
visible (1 second or more) delay to boot in what would be considered the
fast path of the code.

Cc: Patrice CHOTARD <patrice.chotard@st.com>
Cc: Patrick DELAUNAY <patrick.delaunay@st.com>
Link: https://www.spinics.net/lists/devicetree-compiler/msg02972.htmlSigned-off-by: NTom Rini <trini@konsulko.com>
Tested-by: NPatrice Chotard <patrice.chotard@st.com>

Coreutils command nproc can be used on Linux and BSD to count the number of
available CPU cores. Use this instead of relying on the parsing of the
Linux specific proc file system.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

As hinted by GCC 9, there is a return statement that returns
an uninitialized variable in optee_copy_firmware_node().
This patch addresses this.
Signed-off-by: NChristoph Müllner <christoph.muellner@theobroma-systems.com>
Reviewed-by: NHeiko Stuebner <heiko.stuebner@theobroma-systems.com>

Remove incorrect indentation.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

This removes the arch-specific checks for "checkcpu" function from the init
sequence. Make "checkcpu" generic and provide a weak nop stub instead.
Signed-off-by: NOvidiu Panait <ovpanait@gmail.com>

New analysis by the tool has shown that we have some cases where we
weren't handling the error exit condition correctly.  When we ran into
the ENOMEM case we wouldn't exit the function and thus incorrect things
could happen.  Rework the unwinding such that we don't need a helper
function now and free what we may have allocated.

Fixes: 18030d04 ("GPT: fix memory leaks identified by Coverity")
Reported-by: Coverity (CID: 275475, 275476)
Cc: Alison Chaiken <alison@she-devel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Jordy <jordy@simplyhacker.com>
Signed-off-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

This enables readning the cpuid from e-fuse, and deriving a static
MAC address from it.
Signed-off-by: NMark Kettenis <kettenis@openbsd.org>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>

Add alias for mmc/sdmmc so that we can have a fix mmc number for emmc.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>

Rockchip use CONFIG_SPL_OPTEE for OPTEE support, which is load and run
before U-Boot, but not use CONFIG_OPTEE which is after U-Boot.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>

update lpddr3 setting for fix init fail about "col error".
Signed-off-by: NYouMin Chen <cym@rock-chips.com>
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>

Add rk3328-sdram-ddr4-666.dtsi for support ddr4 init.
Signed-off-by: NYouMin Chen <cym@rock-chips.com>
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>

No need to do twice data training for rk3328 ddr sdram, we re-use the
setting for both channel. And adjust the sdram_init properly for correct
init flow.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Signed-off-by: NYouMin Chen <cym@rock-chips.com>

Rockchip has documentation file, doc/README.rockchip but
which is not so readable to add or understand the existing
contents. Even the format that support is legacy readme
in U-Boot.

Add rockchip specific documentation file using new rst
format, which describes the information about Rockchip
supported boards and it's usage steps.

Added minimal information about rk3288, rk3328, rk3368
and rk3399 boards and usage. This would indeed updated
further based on the requirements and updates.

Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>