Signed-off-by: NEric Nelson <eric.nelson@boundarydevices.com>
Acked-by: NStefano Babic <sbabic@denx.de>

When loading a Freescale 2.6.35 on a mx28evk the following issue is seen:

sgtl5000_hw_read: read reg error : Reg 0x00
Device with ID register 0 is not a SGTL5000

Disabling CONFIG_CMD_I2C makes the sgtl5000 probe to succeed.

Mainline kernel does not show this problem.

Until the real cause is not identified, disable 'CONFIG_CMD_I2C' for the
time being.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

The i.MX6 common timer uses the 32-bit variable tbl (time base lower)
to record the overflow of the 32-bit counter. I.e. if the counter
overflows, the variable tbl does overflow, too.

To capture this overflow, use the variable tbu (time base upper), too.
Return the combined value of tbl and tbu.

lastinc is unused then, remove it.
Signed-off-by: NKnut Wohlrab <knut.wohlrab@de.bosch.com>
Signed-off-by: NDirk Behme <dirk.behme@de.bosch.com>
Acked-by: NStefano Babic <sbabic@denx.de>

No need to use multi-line style comments for single-line contents.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: NOtavio Salvador <otavio@ossystems.com.br>

Currently the following kernel hang happens when loading a 2.6.35 kernel from
Freeescale on a mx28evk board:

RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
Bus freq driver module loaded
IMX usb wakeup probe
usb h1 wakeup device is registered
mxs_cpu_init: cpufreq init finished
...

Loading the same kernel using the bootlets from the imx-bootlets-src-10.12.01
package, the hang does not occur.

Comparing the DDR2 initialization from the bootlets code against the U-boot
one, we can notice some mismatches, and after applying the same initialization
into U-boot the 2.6.35 kernel can boot normally.

Also tested with 'mtest' command, which runs succesfully.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Acked-by: NOtavio Salvador <otavio@ossystems.com.br>
Tested-by: NMarek Vasut <marex@denx.de>

When building for the nitrogen boards with 2GiB the following warning happens:

nitrogen6x.c:89:38: warning: integer overflow in expression [-Woverflow]

2GiB can not fit in 32-bits, so use ulong instead.
Reported-by: NAlbert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

Fix the following build error when buildig nitrogen6s1g:

nitrogen6x.c:89:17: error: 'CONFIG_DDR_MB' undeclared (first use in
this function)
nitrogen6x.c:89:17: note: each undeclared identifier is reported only
once for each function it appears in
Reported-by: NAlbert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

Pad config registers exist in APB_MISC_GP space, and control slew
rate, drive strengh, schmidt, high-speed, and low-power modes for
all of the pingroups in Tegra30. This builds off of the pinmux
way of constructing init tables to configure select pads (SDIOCFG,
for instance) during pinmux_init().

Currently, no padcfg entries exist. SDIO3CFG will be added when the
MMC driver is added as per the TRM to work with the SD-card slot on
Dalmore E1611.
Signed-off-by: NTom Warren <twarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

All other Tegra boards have their alias nodes in the .dts file
Signed-off-by: NTom Warren <twarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

The pinmux code issues a warning if the caller attempts to disable the
lock bit in a pinmux register, since this is impossible (once it's
locked, the only way to unlock it is to reset the device/pmt controller).

The I2C/DDC/CEC/USB macros expect a lock setting to be passed in,
and the previous setting of DISABLE caused the pinmux table parsing
code to issue the warning. Changing the lock bits in these table
entries to DEFAULT (i.e. don't touch it) fixes this.
Signed-off-by: NTom Warren <twarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

Differences in padcfg registers (some removed, some added) between
Tegra30 and Tegra114 weren't picked up when I first ported this file.
Signed-off-by: NTom Warren <twarren@nvidia.com>

This caused CAM_MCLK's pinmux reg to be locked out, since the
table parsing code couldn't find a matching entry for VI_ALT3
and wrote garbage to the register.
Signed-off-by: NTom Warren <twarren@nvidia.com>

Enable a common set of partition types, filesystems, and related
commands in tegra-common.h, so that they are available on all Tegra
boards. This allows boot.scr (loaded and executed by the default
built-in environment) on those boards to assume that certain features
are always available.

Do this in tegra-common.h, so that individual board files can undefine
the features if they really don't want any of them.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Various code that is conditional upon HAVE_BLOCK_DEVICE is required by
code conditional upon CONFIG_CMD_PART. So, enable HAVE_BLOCK_DEVICE if
CONFIG_CMD_PART is enabled.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Acked-by: NTom Rini <trini@ti.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

This set of ifdefs is used in a number of places. Move its definition
somewhere common so it doesn't have to be repeated.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Acked-by: NTom Rini <trini@ti.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

All Tegra devices will need CONFIG_BOUNCE_BUFFER. Move it to
tegra-common.h to ensure it's always set.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Tested on my Cardhu-A04 tablet, eMMC and SD-Card work fine, can load
a kernel off of an SD card OK, card detect works, and the env is now
stored in eMMC (end of the 2nd 'boot' sector, same as Tegra20).
Signed-off-by: NTom Warren <twarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

Tegra30 SD/MMC controller differs enough from Tegra20 that it
needs its own entry in the compat_names/compat_id tables and in
the Tegra MMC driver.
Signed-off-by: NTom Warren <twarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

Tegra30 requires the SD Bus Voltage & Power bits be set in the SD
Power Control register. Tegra20 works w/o them set, but do it anyway
for those SoCs as it's part of the SD spec. Also call a common
board pad init routine (pad_init_mmc) in mmc_reset(), used by
Tegra30 only for now.

Note that Tegra20 SD/MMC HW differs enough from Tegra20 that a
new compatible entry is used in the fdt compat_names/id tables.
Signed-off-by: NTom Warren <twarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

T30 requires specific SDMMC pad programming, and bus power-rail bringup.
Signed-off-by: NTom Warren <twarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

Removed SDMMC base addresses from tegra.h since they're no longer used.
Added additional vendor-specific SD/MMC registers and bus power defines.
Signed-off-by: NTom Warren <twarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

Took these values directly from the kernel dts files.
Signed-off-by: NTom Warren <twarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

Pad config registers exist in APB_MISC_GP space, and control slew
rate, drive strengh, schmidt, high-speed, and low-power modes for
all of the pingroups in Tegra30. This builds off of the pinmux
way of constructing init tables to configure select pads (SDIOCFG,
for instance) during pinmux_init().

Currently, only SDIO1CFG is changed as per the TRM to work with
the SD-card slot on Cardhu.

Thanks to StephenW for the suggestion/original idea.
Signed-off-by: NTom Warren <twarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

Use the latest tables & code from our internal U-Boot repo.
The SDMMC3_CD, CLK_LB_IN and CLK_LB_OUT offsets in the pingroup
table were off by a few indices, causing the pinmux init code to
write bad data to the PINMUX_AUX_ regs. This also enabled the lock
bit, which made it impossible to reconfig the pads correctly for
SDMMC3 (SD card on Dalmore) operation. Also fixes SPI_CS2_N,
USB_VBUS_EN0, HDMI_CEC and UART2_RXD/TXD muxes.
Signed-off-by: NTom Warren <twarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

This was an older debug/developmental file that got added
accidentally. Not needed/used in any Cardhu build.
Signed-off-by: NTom Warren <twarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

Minor edit to tegra_car node, add gpio node.
Signed-off-by: NTom Warren <twarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

This wasn't used anywhere in any Tegra build.
Signed-off-by: NTom Warren <twarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

Signed-off-by: NTom Warren <twarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

A Tegra114 HW bug prevents the main CPU vector from being modified under
certain circumstances. Tegra114 A01P and later with a patched boot ROM
set the CPU reset vector to 0x4003fffc (end of IRAM). This allows placing
an arbitrary jump instruction at that location, in order to redirect to
the desired reset vector location. Modify Tegra114's start_cpu() to make
use of this feature. This allows CPUs with the patched boot ROM to boot.

Based-on-work-by: Jimmy Zhang <jimmzhang@nvidia.com>.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Minor edits to clock, apbdma and SPI, make I2C match kernel DT, and add gpio
Signed-off-by: NTom Warren <twarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

Not used, and wrong in Cardhu's case
Signed-off-by: NTom Warren <twarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

tegra_mmc_init() now parses the DT info for bus width, WP/CD GPIOs, etc.
Tested on Seaboard, fully functional.

Tamonten boards (medcom-wide, plutux, and tec) use a different/new
dtsi file w/common settings.
Signed-off-by: NTom Warren <twarren@nvidia.com>
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

Linux dts files were used for those boards that didn't already
have sdhci info populated. Tamonten has their own dtsi file with
common sdhci nodes (sourced from Linux).
Signed-off-by: NTom Warren <twarren@nvidia.com>
Tested-by: NThierry Reding <thierry.reding@avionic-design.de>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

Tamonten boards (medcom-wide, plutux, and tec) use a different/new
dtsi file w/common settings.
Signed-off-by: NTom Warren <twarren@nvidia.com>
Acked-by: NThierry Reding <thierry.reding@avionic-design.de>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

dts Makefile has the arch & board include paths added to DTS_CPPFLAGS.
This allows the use of '#include "xyz"' in the dts/dtsi file which
helps the C preprocessor find common dtsi include files.
Signed-off-by: NTom Warren <twarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

Tested all 5 'buses', i2c probe enumerates device addresses on bus
0, 1 and 2.
Signed-off-by: NTom Warren <twarren@nvidia.com>
Acked-by: NLaxman Dewangan <ldewangan@nvidia.com>

T114, like T30, does not have a separate/different DVC (power I2C)
controller like T20 - all 5 I2C controllers are identical, but
I2C5 is used to designate the controller intended for power
control (PWR_I2C in the schematics). PWR_I2C is set to 400KHz.
Signed-off-by: NTom Warren <twarren@nvidia.com>
Acked-by: NLaxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

T114 has a slightly different I2C clock, with a new (extra) divisor
in standard/fast mode and HS mode. Tested on my Dalmore, and the I2C
clock is 100KHz +/- 3Hz on my Saleae Logic analyzer.

Added a new entry in compat_names for T114 I2C since it differs
from the previous Tegra SoCs. A flag is set when T114 I2C HW is
found so new features like the extra clock divisor can be used.
Signed-off-by: NTom Warren <twarren@nvidia.com>
Acked-by: NLaxman Dewangan <ldewangan@nvidia.com>